A fully-integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2001, Pages 241-244

  Guo, C ^a   Lo, C W ^a   Choi, Y W ^a   Hsu, I ^a   Kan, T ^a   Leung, D ^a   Chan, A ^a   Luong, H C ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC FILTERS; FREQUENCY SYNTHESIZERS; POWER CONTROL; SIGNAL PROCESSING; SPURIOUS SIGNAL NOISE;

IMAGE REJECTION;

RADIO RECEIVERS;

EID: 0034784824     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications
2. A single-chip 900-MHz spread-spectrum wireless transceiver in 1-μm CMOS - Part II: Receiver design
3. A 115-mW, 0.5μm CMOS GPS receiver with wide dynamic-range active filters
4. A 20-mA-receive, 55-mA-transmit, single-chip GSM transceiver in 0.25-μm CMOS
5. A 12.4 mW CMOS frontend for a 5 GHz wireless-LAN receiver
6. A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications