Robust design for VLSI process and device

International Workshop on Statistical Metrology, Proceedings, IWSM

Volumn , Issue , 2001, Pages 7-16

  Chen, M R ^a  

^a UNITED MICROELECTRONICS CORPORATION   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; QUALITY CONTROL; SEMICONDUCTOR DEVICE MANUFACTURE; STATISTICS;

INTEGRATED CIRUIT DESIGN; STANDARD DEVIATION;

VLSI CIRCUITS;

EID: 0034774528     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

1. Signal-to-noise ratios, performance criteria, and transformation
2. A simple method for obtaining resolution IV designs for use with Taguchi's orthogonal arrays
3. Device robust design using multiple-response optimization technique
4. Device optimization using response surface methodology with orthogonal arrays
5. The optimization of multiple-response problems in Taguchi method
6. Optimizing multiple-reponse problems in Taguchi methods by fuzzy multiple attribute decision making
7. VLSI process optimization using Taguchi methods with multiple-criteria approach
8. Optimization of multiple quality responses involving qualitative and quantitative characteristics by applying artificial intelligent neural network