AltiVecTM: Bringing vector technology to the PowerPCTM processor family

1999 IEEE International Performance, Computing and Communications Conference, IPCCC 1999

Volumn , Issue , 1999, Pages 437-444

  Tyler, Jon ^a   Lent, Jeff ^a   Mather, Anh ^a   Nguyen, Huy ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING; COMPUTER SCIENCE;

DATA PARALLELISM; DATA PATHS; FINE GRAINED; MEMORY LATENCIES; MULTIMEDIA APPLICATIONS; PARALLEL OPERATIONS; PREFETCHES; SINGLE PRECISION;

DIGITAL ARITHMETIC;

EID: 0008602329     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PCCC.1999.749469     Document Type: Conference Paper

References (9)

1. Fuller, Sam, "Motorola's AltiVec Technology," http://mot-sps.com/sps/General/altivec-wp.pdf
2. J. Alvarez, E. Barkin, C.-C. Chao, B. Johnson, M. D'Addeo, F. Lassandro, C. Nicoletta, P. Patel, P. Reed, D. Reid, H. Sanchez, J. Siegel, M. Snyder, S. Sullivan, S. Taylor, M. Vo, "A 450MHz PowerPC Microprocessos with Enhanced instruction Set and Copper Interconnect," ISSCC, Feb. 1999.
3. Gwennap, Linley, "G4 Is First PowerPC with AltiVec," Microprocessor Report, pp 17-19, Nov 16, 1998.
4. AltiVec Programming Environments Manual, http:/ /mot-sps.com/sps/General/altivec-pem.pdf
5. Mips Extention for Digital Media with 3D, http:// www.mips.com/Documentation/ isa5-tech-brf.pdf, pp 20-21.
6. S. Vassiliadis, M. Schwarz, B. M. Sung, "Hard-Wired Multipliers with Encoded Partial Products," IEEETrans. on Comp., pp. 1181-1197, Nov. 1991.
7. E. Hokenek, R. K. Montoye, and P. W. Cook, "Second-Generation RISC Floating Point with Multi-ply-Add Fused," IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, pp. 1207-1213, Oct. 1990.
8. IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Standard 754-1985.
9. M. J. Schulte, J. Omar, and E. E. Swartzlander, Jr., "Optimal Initial Approximations for the Newton-Raphson Division Algorithm," Computing, vol.53, pp. 233-244, 1994.