Partitioned systolic architecture for modular multiplication in GF(2m)

Information Processing Letters

Volumn 76, Issue 3, 2000, Pages 135-139

  Kim, Hyun Sung ^a   Lee, Sung Woo ^a   Yoo, Kee Young ^a  

^a Kyungpook National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

MULTIPLYING CIRCUITS; SYSTOLIC ARRAYS;

MODULAR MULTIPLICATION;

DIGITAL ARITHMETIC;

EID: 0034548584     PISSN: 00200190     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0020-0190(00)00130-7     Document Type: Article

References (5)

1. Rivest R.L., Shamir A., Adleman L. A method for obtaining digital signatures and public-key cryptosystems. Comm. ACM. Vol. 21:1978;120-126.
2. m). IEEE Trans. Circuits Systems. Vol. 38:1991;796-800.
3. Jain S.K., Song L., Parhi K.K. Efficient semisystolic architectures for finite-field arithmetic. IEEE Trans. on VLSI Systems. Vol. 6:(1):1998;101-113.
4. Kung S.Y. VLSI Array Processors. 1987;Prentice-Hall, Englewood Cliffs, NJ.
5. Yoo K.Y. A systolic array design methodology for sequential loop algorithms. Ph.D. Thesis:1992;Rensselaer Polytechnic Institute, Troy, NY.