Programmable and low power VLSI architectures for full search motion estimation in multimedia communications

IEEE International Conference on Multi-Media and Expo

Volumn , Issue III/WEDNESDAY, 2000, Pages 1395-1398

  Fanucci, L ^a   Bertini, L ^a   Saponara, S ^a  

^a CNR   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; MOTION ESTIMATION; MULTIMEDIA SYSTEMS; SIGNAL TO NOISE RATIO; WIRELESS TELECOMMUNICATION SYSTEMS;

BLOCK-MATCHING (BM) ALGORITHMS;

VLSI CIRCUITS;

EID: 0034508667     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. Predictive coding based on efficient motion estimation
2. Motion compensated interframe image prediction
3. A new three-step search algorithm for block motion estimation
4. Predictive RD optimized motion estimation for very low bit-rate video coding
5. VLSI architectures for video compression - A Survey
6. Bit serial architecture for real time motion compensation
7. A family of VLSI designs for the motion compensation block matching algorithms
8. A dedicated circuit for real time motion compensation
9. A high performance full motion video compression chip set
10. High-throughput B-M VLSI architecture with low memory bandwidth
11. Parametrizable VLSI architectures for the full-search block-matching algorithm
12. VLSI architecture for block-matching motion estimation algorithm
13. High-throughput, low complexity, parametrizable VLSI architecture for full search block matching algorithm for advanced multimedia applications