High-throughput, low complexity, parametrizable VLSI architecture for full search block matching algorithm for advanced multimedia applications

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 1999, Pages 1479-1482

  Fanucci, L ^a   Saletti, R ^b   Bertini, L ^b   Moio, P ^b   Saponara, S ^b  

^a CNR   (Italy)

^b UNIVERSITY OF PISA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CLOCKS; CMOS INTEGRATED CIRCUITS; IMAGE CODING; IMAGE MATCHING; THROUGHPUT; VLSI CIRCUITS;

CLOCK FREQUENCY; CMOS TECHNOLOGY; FULL SEARCH ALGORITHM; FULL SEARCH BLOCK MATCHING ALGORITHM; HARDWARE COMPLEXITY; HIGH THROUGHPUT; MULTIMEDIA APPLICATIONS; VLSI ARCHITECTURES;

MOTION ESTIMATION;

EID: 0006423387     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.1999.814449     Document Type: Conference Paper

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