A VLSI architecture for IWT (Integer Wavelet Transform)

Midwest Symposium on Circuits and Systems

Volumn 3, Issue , 2000, Pages 1174-1177

  Martina, M ^a   Masera, G ^a   Piccinini, G ^a   Zamboni, M ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; IMAGE COMPRESSION; MATHEMATICAL MODELS; MATRIX ALGEBRA; OPTIMIZATION; VLSI CIRCUITS;

INTEGER WAVELET TRANSFORM; OPTIMAL FACTORIZATION; POLYPHASE;

WAVELET TRANSFORMS;

EID: 0034465166     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Factoring wavelet transforms into lifting steps
2. The lifting scheme: A construction of second generation wavelets
3. VLSI implementation of discrete wavelet transform
4. Wavelet transforms that map integers to integers
5. Lifting integer wavelets towards linearity
6. Minimally non-linear integer wavelets for image coding
7. Wavelet filter evaluation for image compression
8. A novel VLSI architecture for integer wavelet transform via lifting scheme