A 2.5MSample/s multi-bit ΔΣ CMOS ADC with 95dB SNR

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 336-337

  Geerts, Y ^a   Steyaert, M ^a   Sansen, W ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL TO ANALOG CONVERSION; FEEDBACK; MONTE CARLO METHODS; SIGNAL TO NOISE RATIO; SPURIOUS SIGNAL NOISE;

DYNAMIC ELEMENT MATCHING (DEM);

ANALOG TO DIGITAL CONVERSION;

EID: 0034428325     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Linearity enhancement of multibit ΣΔ A/D and D/A converters using data weighted averaging
2. Flash A/D specifications of multi-bit ΣΔ A/D converters
3. A 3.3 V 15-bit delta-sigma ADC with a signal bandwith of 1.1 MHz for ADSL-applications
4. A fast-settling CMOS Op amp for SC circuits DC gain