BIST TPG for combinational cluster interconnect testing at board level

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 16, Issue 5, 2000, Pages 427-442

  Chiang, Chen Huan ^a   Gupta, Sandeep K ^b  

^a NOKIA RESEARCH CENTER   (United States)

^b University of Southern California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; COMBINATORIAL CIRCUITS; ELECTRIC FAULT CURRENTS; INTERCONNECTION NETWORKS; LOGIC DESIGN; PRINTED CIRCUIT DESIGN; PRINTED CIRCUIT TESTING;

BOUNDARY SCAN CELLS (BSC); TEST PATTERN GENERATORS (TPG);

PRINTED CIRCUIT BOARDS;

EID: 0034298578     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008308430051     Document Type: Article

References (15)

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