Interaction among cost functions in placement

ICVC 1999 - 6th International Conference on VLSI and CAD

Volumn , Issue , 1999, Pages 32-36

  Sarrafzadeh, Majid ^a   Wang, Maogang ^a  

^a Northwestern University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84950161484     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVC.1999.820812     Document Type: Conference Paper

References (17)

1. C. Alpert. "The ISPD98 Circuit Benchmark Suite". In International Symposium on Physical Design, pages 18-25. ACM, April 1998.
2. C. J. Alpert, J. H. Huang, and A. B. Kahng. "Multilevel Circuit Partitioning". In Design Automation Conference, pages 530-533. IEEE/ACM, 1997.
3. J. Cong, H. P. Li, S. K. Lim, T. Shibuya, and D. Xu. "Large Scale Circuit Partitioning with Loose/Stable Net Removal and Signal Flow Based Clustering". In International Conference on Computer-Aided Design, pages 441-446. IEEE, 1997.
4. A. E. Dunlop and B. W. Kernighan. "A Procedure for Placement of Standard Cell VLSI Circuits". IEEE Transactions on Computer Aided Design, 4(l):92-98, January 1985.
5. D. Dutt and W. Deng. "VLSI Circuit Partitioning by Cluster-Removal Using Iterative Impro vement Techniques". In International Conference on Computer-Aided Design, pages 194-200. IEEE, 1996.
6. S. Hauck and G. Boriello. "An Evaluation of Bipar-titioning Techniques". In Chapel Hill Conference on Advanced Research in VLSI, 1995.
7. D. Huang and A. B. Kahng. "Partitioning-based Standard-cell Global Placement with an Exact Ob jec-tive". In International Symposium on Physical Design, pages 18-25. ACM, April 1997.
8. G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar. "Multilevel Hypergraph Partitioning: Application in VLSI Domain". In Design Automation Conference, pages 526-529. IEEE/ACM, 1997.
9. G. Karypis and V. Kumar. "Multilevel k-way Hypergraph Partitioning". In Design Automation Conference, pages 343-348, 1999.
10. J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich. "GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization". IEEE Transactions on Computer Aided Design, 10(3);365-365, 1991.
11. S. Mayrhofer and U. Lauther. "Congestion-Driven Placement Using a New Multi-Partitioning Heurist ic". In International Conference on Computer-Aided Design, pages 332-335. IEEE/ACM, November 1990.
12. P. N. Parakh, R. B. Brown, and K. A. Sakallah. "Congestion Driven Quadratic Placement". In Design Automation Conference, pages 275-278. IEEE/ACM, 1998.
13. M. Sarrafzadeh and M. Wang. "NRG: Global and Detailed Placement". In International Conference on Computer-Aided Design. IEEE, November 1997.
14. C. Sechen. VLSI Placement and Global Routing Using Simulated Annealing. Kluwer, B. V., Deventer, The Netherlands, 1988.
15. C. Sechen and K. W. Lee. "An Improved Simulated Annealing Algorithm for Row-Based Placement". In Design Automation Conference, pages 180183. IEEE/ACM, 1988.
16. G. Sigl, K. Doll, and F. M. Johannes. "Analytical Placement: A Linear or a Quadratic Objective Function". In Design Automation Conference, pages 427431. IEEE/ACM, 1991.
17. M. Wang and M. Sarrafzadeh. "Behavior of Congestion Minimization During Placement". In International Symposium on Physical Design, pages 145-150. ACM, April 1999.