Implementation of modeling and simulation in semiconductor wafer fabrication with time constraints between wet etch and furnace operations

IEEE Transactions on Semiconductor Manufacturing

Volumn 13, Issue 3, 2000, Pages 273-277

  Scholl, Wolfgang ^a   Domaschke, Joerg ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL VAPOR DEPOSITION; COMPUTER SIMULATION; ETCHING; INDUSTRIAL FURNACES; INDUSTRIAL MANAGEMENT; PLANNING; SCHEDULING;

DISCRETE EVENT SIMULATION; SEMICONDUCTOR WAFER FABRICATION; TIME BOUND SEQUENCES; TIME CONSTRAINTS; WET ETCH;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0034249293     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.857935     Document Type: Article

References (6)

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3. J. W. Fowler and J. K. Robinson, Measurement and improvement of manufacturing capacity (MIMAC), project final report, SEMATECH Tech. Transfer 95062861A-TR.
4. W. J. Hopp and M. L. Spearman, Factory Physics: Foundations of Manufacturing Management. Chicago, IL: Irwin, 1996.
5. J. K. Robinson and R. Giglo, "Capacity planning for semiconductor wafer fabrication with time constraints between operations," in Proc. 1999 Winter Simulation Conf., 1999, pp. 880-887.
6. J. P. Winz and P. T. Lim, "Improvement of production logistics for backend manufacturing," in Conf. Proc. 1999 IEEE Int. Symp. Semiconductor Manufacturing, 1999, pp. 81-84.