An analytical model of multiple ILD thickness variation induced by interaction of layout pattern and CMP process

IEEE Transactions on Semiconductor Manufacturing

Volumn 13, Issue 3, 2000, Pages 286-292

  Ouyang, Charles ^a,b,f   Ryu, Kyungsuk ^a,c,f   Milor, Linda ^d,e,f   Maly, Wojciech ^a,f   Hill, Gene ^d   Peng, Yeng Kaung ^d  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b DFM/DFT Group of Level One Communications   (United States)

^c INTEL CORPORATION   (United States)

^d ADVANCED MICRO DEVICES   (United States)

^e eSilicon Corporation   (United States)

^f IEEE   (United States)

Author keywords

Chemical mechanical polishing; Dielectric variation; Pattern dependencies; Physical model

Indexed keywords

CHEMICAL POLISHING; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; DIELECTRIC MATERIALS; FAST FOURIER TRANSFORMS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS;

CHEMICAL MECHANICAL POLISHING; HYDRODYNAMIC PRESSURE; INTERLAYER DIELECTRIC;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034248378     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.857937     Document Type: Article

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