-
1
-
-
84937078021
-
Signed-Digit Number Representations for Fast Parallel Arithmetic
-
A. Avizienis, "Signed-Digit Number Representations for Fast Parallel Arithmetic," IRE Trans. Electronic Computers, vol. 10, pp. 389-400, 1961.
-
(1961)
IRE Trans. Electronic Computers
, vol.10
, pp. 389-400
-
-
Avizienis, A.1
-
3
-
-
0022121184
-
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
-
Sept.
-
N. Takagi, H. Yasuura, and S. Yajima, "High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree," IEEE Trans. Computers, vol. 34, no. 9, pp. 789-796, Sept. 1985.
-
(1985)
IEEE Trans. Computers
, vol.34
, Issue.9
, pp. 789-796
-
-
Takagi, N.1
Yasuura, H.2
Yajima, S.3
-
4
-
-
0023170517
-
Design of High Speed MOS Multiplier and Divider Using Redundant Binary Representation
-
S. Kuninobu, T. Nishiyama, H. Edamatsu, T. Taniguchi, and N. Takagi, "Design of High Speed MOS Multiplier and Divider Using Redundant Binary Representation," Proc. Eighth Symp. Computer Arithmetic, pp. 80-86, 1987.
-
(1987)
Proc. Eighth Symp. Computer Arithmetic
, pp. 80-86
-
-
Kuninobu, S.1
Nishiyama, T.2
Edamatsu, H.3
Taniguchi, T.4
Takagi, N.5
-
5
-
-
0023293750
-
A High-Speed Multiplier Using a Redundant Binary Adder Tree
-
Y. Harata, Y. Nakamura, H. Nagase, M. Takigawa, and N. Takagi, "A High-Speed Multiplier Using a Redundant Binary Adder Tree," IEEE J. Solid-State Circuits, vol. 22, no. 1, pp. 28-34, 1987.
-
(1987)
IEEE J. Solid-State Circuits
, vol.22
, Issue.1
, pp. 28-34
-
-
Harata, Y.1
Nakamura, Y.2
Nagase, H.3
Takigawa, M.4
Takagi, N.5
-
6
-
-
0025448597
-
A New Carry-Free Division Algorithm and Its Application to a Single-Chip 1024-b RSA Processor
-
A. Vandemeulebroecke, E. Vanzieleghem, T. Denayer, and P.G.A. Jespers, "A New Carry-Free Division Algorithm and Its Application to a Single-Chip 1024-b RSA Processor," IEEE J. Solid-State Circuits, vol. 25, no. 3, pp. 748-755, 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, Issue.3
, pp. 748-755
-
-
Vandemeulebroecke, A.1
Vanzieleghem, E.2
Denayer, T.3
Jespers, P.G.A.4
-
8
-
-
0026679534
-
An Efficient Redundant-Binary Number to Binary Number Converter
-
S.M. Yen, C.S. Laih, C.H. Chen, and J.Y. Lee, "An Efficient Redundant-Binary Number to Binary Number Converter," IEEE J. Solid-State Circuits, vol. 27, no. 1, pp. 109-112, 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, Issue.1
, pp. 109-112
-
-
Yen, S.M.1
Laih, C.S.2
Chen, C.H.3
Lee, J.Y.4
-
9
-
-
0017930809
-
A Method for Obtaining Digital Signatures and Public-Key Cryptosystems
-
R.L. Rivest, A. Shamir, and L.M. Adleman, "A Method for Obtaining Digital Signatures and Public-Key Cryptosystems," Comm. ACM, vol. 21, no. 2, pp. 120-126, 1978.
-
(1978)
Comm. ACM
, vol.21
, Issue.2
, pp. 120-126
-
-
Rivest, R.L.1
Shamir, A.2
Adleman, L.M.3
-
10
-
-
0003683288
-
High-Speed RSA Implementations
-
RSA Laboratories, Nov.
-
Ç.K. Koç, "High-Speed RSA Implementations," Technical Report TR 201, RSA Laboratories, Nov. 1994.
-
(1994)
Technical Report TR 201
-
-
Koç, Ç.K.1
-
12
-
-
0009399673
-
Computing Sequences with Addition Chains
-
P. Downey, B. Leong, and R. Sethi, "Computing Sequences with Addition Chains," SIAM J. Computing, vol. 10, pp. 638-646, 1981.
-
(1981)
SIAM J. Computing
, vol.10
, pp. 638-646
-
-
Downey, P.1
Leong, B.2
Sethi, R.3
-
14
-
-
84874800178
-
A Public Key Cryptosystem and a Signature Scheme Based on Discrete Logarithms
-
T. ElGamal, "A Public Key Cryptosystem and a Signature Scheme Based on Discrete Logarithms," IEEE Trans. Information Theory, vol. 31, no. 4, pp. 469-472, 1985.
-
(1985)
IEEE Trans. Information Theory
, vol.31
, Issue.4
, pp. 469-472
-
-
Elgamal, T.1
-
16
-
-
0001498499
-
Fast Exponentiation with Precomputation: Algorithms and Lower Bounds
-
preprint, Mar. An earlier version appeared
-
E.F. Brickell, D.M. Gordon, K.S. McCurley, and D.R. Wilson, "Fast Exponentiation with Precomputation: Algorithms and Lower Bounds," preprint, Mar. 1995. An earlier version appeared in Proc. EUROCRYPT '92.
-
(1995)
Proc. EUROCRYPT '92
-
-
Brickell, E.F.1
Gordon, D.M.2
McCurley, K.S.3
Wilson, D.R.4
-
17
-
-
0000266095
-
Speeding Up the Computations on an Elliptic curve Using Addition-Subtraction Chains
-
F. Morain and J. Olivos, "Speeding Up the Computations on an Elliptic curve Using Addition-Subtraction Chains," Theoretical Informatics and Applications, vol. 24, pp. 531-543, 1990.
-
(1990)
Theoretical Informatics and Applications
, vol.24
, pp. 531-543
-
-
Morain, F.1
Olivos, J.2
-
20
-
-
0024715942
-
Minimum Weight Modified Signed-Digit Representations and Fast Exponentiation
-
J. Jedwab and C. Mitchell, "Minimum Weight Modified Signed-Digit Representations and Fast Exponentiation," Electronics Letters, vol. 25, pp. 1,171-1,172, 1989.
-
(1989)
Electronics Letters
, vol.25
-
-
Jedwab, J.1
Mitchell, C.2
-
22
-
-
0028764220
-
Exponentiation Using Canonical Recoding
-
Ö. Egecioglu and ÇK. Koç, "Exponentiation Using Canonical Recoding," Theoretical Computer Science, vol. 129, no. 2, pp. 407-417, 1994.
-
(1994)
Theoretical Computer Science
, vol.129
, Issue.2
, pp. 407-417
-
-
Egecioglu, Ö.1
Koç, Ç.K.2
-
23
-
-
0029358884
-
The Montgomery Inverse and Its Applications
-
Aug.
-
B.S. Kaliski, "The Montgomery Inverse and Its Applications," IEEE Trans. Computers, vol. 44, no. 8, pp. 1,064-1,065, Aug. 1995.
-
(1995)
IEEE Trans. Computers
, vol.44
, Issue.8
-
-
Kaliski, B.S.1
-
24
-
-
0027644786
-
Signed Digit Representations of Minimal Hamming Weight
-
Aug.
-
S. Arno and F.S. Wheeler, "Signed Digit Representations of Minimal Hamming Weight," IEEE Trans. Computers, vol. 42, no. 8, pp. 1,007-1,010, Aug. 1993.
-
(1993)
IEEE Trans. Computers
, vol.42
, Issue.8
-
-
Arno, S.1
Wheeler, F.S.2
-
25
-
-
0000490812
-
A Survey of Fast Exponentiation Methods
-
D.M. Gordon, "A Survey of Fast Exponentiation Methods," J. Algorithms, vol. 27, pp. 129-146, 1998.
-
(1998)
J. Algorithms
, vol.27
, pp. 129-146
-
-
Gordon, D.M.1
-
26
-
-
0015682806
-
On Arithmetic Weight for a General Radix Representation of Integers
-
W.E. Clark and J.J. Liang, "On Arithmetic Weight for a General Radix Representation of Integers," IEEE Trans. Information Theory, vol. 19, pp. 823-826, 1973.
-
(1973)
IEEE Trans. Information Theory
, vol.19
, pp. 823-826
-
-
Clark, W.E.1
Liang, J.J.2
-
27
-
-
0031075081
-
m)
-
Feb.
-
m)," IEEE Trans. Computers, vol. 46, no. 2, pp. 162-172, Feb. 1997.
-
(1997)
IEEE Trans. Computers
, vol.46
, Issue.2
, pp. 162-172
-
-
Wu, H.1
Hasan, M.A.2
-
28
-
-
85037485395
-
-
"Computational Method and Apparatus for Finite Field Arithmetic," U.S. Patent #4,587,627, 1986
-
J. Omura and J. Massey, "Computational Method and Apparatus for Finite Field Arithmetic," U.S. Patent #4,587,627, 1986.
-
-
-
Omura, J.1
Massey, J.2
-
29
-
-
0030261826
-
Parallel Canonical Recoding
-
Ç.K. Koç, "Parallel Canonical Recoding," Electronics Letters, vol. 32, pp. 2,063-2,065, 1996.
-
(1996)
Electronics Letters
, vol.32
-
-
Koç, Ç.K.1
-
30
-
-
0004205671
-
-
E.E. Swartzlander Jr., ed., IEEE CS Press
-
Computer Arithmetic, E.E. Swartzlander Jr., ed., vols. 1 and 2. IEEE CS Press, 1990.
-
(1990)
Computer Arithmetic
, vol.1-2
-
-
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