Parallel canonical recoding

Electronics Letters

Volumn 32, Issue 22, 1996, Pages 2063-2065

  Koc C K ^a  

^a 1148 Kelley Engineering Center Corvallis   (United States)

Author keywords

Arithmetic codes; Codes; Parallel algorithms

Indexed keywords

BINARY CODES; DIGITAL ARITHMETIC; ENCODING (SYMBOLS); VECTORS;

PARALLEL CANONICAL RECODING;

PARALLEL ALGORITHMS;

EID: 0030261826     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19961402     Document Type: Article

References (6)

1. BRENT, R.P., and KUNG, H.T.: 'A regular layout for parallel adders', IEEE Trans., 1982, COM-31, (3), pp. 260-264
2. EGECIOGLU, Ö., and KOÇ, K.: 'Exponentiation using canonical receding', Theoretical Computer Science, 1994, 129, (2), pp. 407-417
3. KAI-HWANG: 'Computer arithmetic, principles, architecture, and design' (John Wiley & Sons, New York, 1989)
4. KOREN, U.: 'Computer arithmetic algorithms' (Prentice-Hall, Englewood Cliffs, NJ, 1993)
5. LADNER, R., and FISCHER, M.: 'Parallel prefix computation', J. ACM, 1980, 27, (4), pp. 831-838
6. REITWIESNER, G.W.: 'Binary arithmetic', Advances in Computers, 1960, 1, pp. 231-308