Resist removal process in dual damascene structure integrating Cu and SiLK for 0.18 μm technology

Microelectronic Engineering

Volumn 53, Issue 1, 2000, Pages 381-384

  Louis, D ^a   Arvet, C ^a   Lajoinie, E ^a   Peyne, C ^b   Lee, S ^b   Berry, I ^c   Han, Q ^c  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

^c EATON CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL OPERATIONS; COPPER; DIELECTRIC MATERIALS; ETCHING; MASKS; PHOTORESISTS; SILICON COMPOUNDS;

RESIST REMOVAL; SELF ALIGNED DUAL DAMASCENE; WET CHEMICAL STRIP PROCESSES;

MICROELECTRONIC PROCESSING;

EID: 0034207067     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(00)00338-5     Document Type: Article

References (6)

1. 1- A. Blosse and al, " PVD aluminum dual damascene interconnection: Yield comparison between counterbore and self aligned approaches", IITC 1999, pp. 215-217.
2. 2- P. Singer "Dual damascene challenges dielectric etch", Semiconductor International, August 99.
3. 3- Q. Han, M. Dahimene, P. Sakthivel, R, Mohondro, I. Berry, "Achieving highly selective resist strip and residue removal over low-k dielectrics", Future Fab International, 7, P 219, 1999
4. 4- W. M. Lee, "A proven sub-μm photoresist stripper solution for post metal and via hole processes", J. of Electrochem. Society, vol. 93-25, 1993.
5. 5- D. Louis and al, "Improved post etch cleaning for low-k and copper integration for 0.18 μm technology", MNE, 1998.
6. 6- O. Demolliens and al, "copper-siLK® integration in 0.18 μm double level metal interconnect", IITC 1999.