A systolic image difference algorithm for RLE-compressed images

IEEE Transactions on Parallel and Distributed Systems

Volumn 11, Issue 5, 2000, Pages 433-443

  Ercal, Fikret ^a,b   Allen, Mark ^c   Feng, Hao ^d  

^a IEEE   (United States)

^b University of Missouri Rolla   (United States)

^c HEWLETT PACKARD COMPANY   (United States)

^d MICROSOFT   (United States)

Author keywords

Image compression; Image difference; Run length encoding; Systolic algorithm

Indexed keywords

IMAGE DIFFERENCE; RUN-LENGTH ENCODING (RLE);

COMPUTATIONAL COMPLEXITY; IMAGE ANALYSIS; IMAGE CODING; IMAGE QUALITY; SYSTOLIC ARRAYS;

IMAGE COMPRESSION;

EID: 0034187248     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/71.852397     Document Type: Article

References (14)

1. P.P. Jonker and E.R. Komen, "A Scalable Real-Time Image Processing Pipeline," Proc. 11th Int'l Conf. Pattern Recognition (IAPR), vol. 4, 1992. Conference D: Architectures for Vision and Pattern Recognition, pp. 142-146.
2. F. Ercal, F. Bunyak, F. Hao, and L. Zheng, "A Fast Modular RLE-Based Inspection Scheme for PCBs," Proc. Int'l Society for Optical Eng., (SPIE) - Architectures, Networks, and Intelligent Systems for Manufacturing Integration, vol. 3,203, pp. 49-59, Oct. 1997.
3. S. Gil, R. Milanese, and T. Pun, "Comparing Features for Target Tracking in Traffic Scenes," Pattern Recognition, vol. 29, no. 8, pp. 1,285-1,296, 1996.
4. H. Kawasumi, H. Sekii, N. Enomoto, H. Ohata, and A. Okazaki, "Detecting Intruders using Time-Series Data by Projection Pattern of Silhouette," Electrical Engineering in Japan, vol. 119, no. 1, pp. 62-73, 1997.
5. G.M. Emelyanov, N.V. Kurmyshev, and O.Y. Yuvzhik, "Procedures and Algorithms for Detecting and Determining the Orientation of Objects in Binary Images," Pattern Recognition and Image Analysis, vol. 7, no. 3 pp. 373-378, 1997.
6. G. Agam, J. Frydman, O. Amiram, and I. Dinstein, "Efficient Morphological Processing of Maps and Line-Drawings Based on Directional Interval Coding," Proc. SPIE - The Int'l Soc. for Optical Eng., vol. 3,168 pp. 41-51, 1997.
7. N.K. Ratha, A.K. Jain, and D.T. Rover, "Convolution on Splash 2," Proc. IEE Symp. FPGAs for Custom Computing Machines, Apr. 1995.
8. A. Rasquinha and N. Ranganathan, "C3L: A Chip for Connected Component Labelling," IEEE 10th International Conf. VLSI Design, pp. 446-51, Jan. 1997.
9. M. Djunatan and T. Mengko, "A Programmable Real-Time Systolic Processor Architecture for Image Morphological Operations, Binary Template Matching and Min/Max Filtering," 1991 IEEE Int'l Symp. Circuits and Systems, vol. 1, pp. 65-68, 1991.
10. N. Ranganathan and K.B. Doreswamy, "A Systolic Algorithm and Architecture for Image Thinning," Proc. 5th Great Lakes Symp. VLSI, Mar 1995.
11. Vipin Kumar, A. Grama, A. Gupta, and G. Karypis, Intro. to Parallel Computing: Design and Analysis of Algorithms. Benjamin/ Cummings Publishing Company Inc., 1994.
12. Y. Ben-Asher, D. Peleg, R. Ramaswami, and A. Schuster, "The Power of Reconfiguration," J. Parallel Distributed Computing, vol. 13, pp. 139-153, 1991.
13. F. Ercal, H. Pottinger, V.S. Balakrishnan, and M. Agarwal, "Design and Implementation of a Systolic Array Based RLE Image Processor Using an FPGA," http://vision1.cs.umr.edu/ ∼systolic/Project/detail.html.
14. J.V. Oldfield and R.C. Dorf, Field Programmable Gate Arrays. John Wiley and Sons, Inc., 1995.