Cache memory design for Internet processors

IEEE Micro

Volumn 20, Issue 1, 2000, Pages 28-33

  Chiueh, Tzi Cker ^a   Pradhan, Prashant ^a  

^a USA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER STORAGE; COMPUTER ARCHITECTURE; MERGING; NETWORK PROTOCOLS; PACKET NETWORKS; ROUTERS; TABLE LOOKUP;

HOST ADDRESS CACHE (HAC); INTELLIGENT HOST ADDRESS RANGE CACHE (IHARC); INTERNET PROCESSORS; INTERNET PROTOCOLS (IP);

INTERNET;

EID: 0033886439     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.820050     Document Type: Article

References (6)

1. W. Doeringer, G. Karjoth, and M. Nassehi, "Routing on Longest Matching Prefixes," IEEE/ACM Transactions on Networking, Vol. 4, No.1, Feb. 1996, pp.86-97.
2. M. Waldvogel, et al., "Scalable High Speed IP Routing Lookups," Proc. ACM Sigcomm 97, ACM Press, New York, 1997, pp.3-14.
3. V. Srinivasan and G. Varghese, "Faster IP Lookups Using Controlled Prefix Expansion," Proc. ACM Sigmetrics, ACM Press, 1998, pp. 1-10.
4. T. Chiueh and P. Pradhan, "High Performance IP Routing Table Lookup using CPU Caching," Proc. IEEE Infocom 99, IEEE, New York, 1999, pp 1421-1428.
5. T. Chiueh and P. Pradhan, "Cache Memory Design for Network Processors," Proc. IEEE HPCA-6, IEEE Computer Society, Los Alamitos, Calif., 2000.
6. Michigan University and Merit Network, "Internet Performance Measurement and Analysis (IPMA) Project"; http://nic.merit.edu/ipma.