Reasoning about analog-level implementations of digital systems

Formal Methods in System Design

Volumn 16, Issue 2, 2000, Pages 127-158

  Hanna, Keith ^a  

^a UNIVERSITY OF KENT   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC POTENTIAL; FORMAL LOGIC; GATES (TRANSISTOR); LOGIC GATES; SPECIFICATIONS; SYSTEMS ANALYSIS;

DIGITAL SYSTEMS; HIGHER ORDER LOGIC;

DIGITAL CIRCUITS;

EID: 0033876859     PISSN: 09259856     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008791128550     Document Type: Article

References (17)

1. D. A. Basin, "Verification of combinational logic in Nuprl," in M. Leeser and G. Brown (Eds.), Hardware Specification, Verification and Synthesis: Mathematical Aspects, Springer Verlag, 1990. LNCS, Vol. 408, pp. 333-357.
2. R. Boute, "Funmath illustrated; a declarative formalism and application examples," Technical Report, Department of Informatics, Katholieke Universiteit Nijmegen, July 1993.
3. G. M. Brown and M. E. Leeser, "From programs to transistors: Verifying hardware synthesis tools," in M. Leeser and G. Brown (Eds.), Hardware Specification, Verification and Synthesis: Mathematical Aspects, Springer Verlag, 1990. LNCS, Vol. 408, pp. 129-15.
4. M. Gordon, "Why higher-order logic is a good formalism for specifying and verifying hardware," in G.J. Milner and P.A. Subrahmanyam (Eds.), Formal Aspects of VLSI Design: Proc. of the 1985 Edinburgh Workshop on VLSI, North-Holland, pp. 153-177, 1986.
5. M. Gordon, P. Loewenstein, and M. Shahaf, "Formal verification of a cell library," in L.J.M. Claesen (Ed.), VLSI Design Methods II, Elsevier Science Publishers B.V., 1990, pp. 409-417.
6. F.K. Hanna and N. Daeche, "Specification and verification of digital systems using higher-order logic," Proc. IEE, Part E, pp. 242-254, 1986.
7. F.K. Hanna and N. Daeche, "Specification and verification using higher-order logic: A case study," in Milne and Subrahmanyam (Eds.), Formal Aspects of VLSI Design, North Holland, 1986, pp. 179-213.
8. K. Hanna, "Reasoning about real digital circuits," in Proc Higher Order Logic Theorem Proving and its Applications, Springer-Verlag, 1994.
9. K. Hanna, "Automatic verification of mixed-level logic circuits," in G. Gopalakrishnan and P. Windley (Eds.), Formal Methods in Computer-Aided Design; FMCAD 98, Springer-Verlag, 1998, pp. 133-148.
10. C.A.R. Hoare, "A theory for the derivation of combinational C-mos circuit designs," Theoretical Computer Science, Vol. 90, pp. 235-251, 1991.
11. D.A. Hodges and H.G. Jackson, Analysis and Design of Digital Integrated Circuits, McGraw-Hill, 1983.
12. IEEE-DASC, "IEEE standard VHDL-AMS language reference manual," Technical Report Draft IEEE Std 1076.1-1997, IEEE Computer Society, 1997.
13. T. Melham, Higher Order Logic and Hardware Verification, Cambridge University Press, 1993.
14. R.E. Shostak, "On the SUP-INF method for proving Presburger formulas," ACM, Vol. 24, No. 4, pp. 529-543, 1977.
15. R.E. Shostak, "Formal verification of circuit designs," in T. Uehara and M. Barbacci (Eds.), Computer Hardware Description Languages and their Applications, North-Holland, 1983, pp. 13-30.
16. D. Weise, "Constraints, abstraction and verification," in M. Leeser and G. Brown (Eds.), Hardware Specification, Verification and Synthesis: Mathematical Aspects, Springer Verlag, 1989. LNCS, Vol. 408, pp. 25-39.
17. G. Winskel, "Models and logic of MOS circuits," in M. Broy (Ed.), Logic of Programming and Calculi of Discrete Design, Springer-Verlag, 1987. NATO ASI series, Vol. F36, pp. 367-413.