Reduction of the parasitic charge generation during silicon nitride deposition in a LOCOS isolation without field implant

Microelectronics Reliability

Volumn 40, Issue 4-5, 2000, Pages 593-596

  Fay, J L ^a,b,c   Beluch, J ^a   Despax, B ^b   Bafleur, M ^c   Sarrabayrouse, G ^c  

^a MOTOROLA INC   (United States)

^b Lab de Genie Elec de Toulouse   (France)

^c LAAS CNRS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DIFFUSION IN SOLIDS; ELECTRIC INSULATION; ION IMPLANTATION; LEAKAGE CURRENTS; OXIDATION; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SEMICONDUCTING SILICON; SEMICONDUCTOR DOPING; SILICON NITRIDE; THRESHOLD VOLTAGE;

LOW PRESSURE CHEMICAL VAPOR DEPOSITION (LPCVD);

MOSFET DEVICES;

EID: 0033742172     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/s0026-2714(99)00269-3     Document Type: Article

References (3)

1. Fay JL, Beluch J, Allirand L, Brosset D, Despax B, Bafleur M, Sarrabayrouse G. Comprehensive analysis of an isolation area obtained by local oxidation of silicon without field implant. Jpn J Appl Phys 1999;38(9A): 5012-7.
2. Wolf S. A review of isolation technologies - part 4. Solid State Technology, 1992.
3. Butler J, Allen G, Hall A, Nowak R. Electrical characterization of doped and undoped PECVD oxides. VMIC Conference. Santa Clara, USA, 1990. p. 387-9.