Cache memories

IEEE Potentials

Volumn 19, Issue 2, 2000, Pages 24-29

  Stacpoole, Richard ^a   Jamil, Tariq ^a  

^a UNIVERSITY OF TASMANIA   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; COMPUTER ARCHITECTURE; COMPUTER SYSTEMS; DATA STORAGE EQUIPMENT; DATA TRANSFER; PERFORMANCE; RESPONSE TIME (COMPUTER SYSTEMS);

CENTRAL PROCESSING UNIT; DIRECT MAPPED CACHE; FULLY ASSOCIATIVE CACHE; LEAST RECENTLY USED LINE REPLACEMENT ALGORITHM; SPATIAL LOCALITY; TEMPORAL LOCALITY;

BUFFER STORAGE;

EID: 0033730522     PISSN: 02786648     EISSN: None     Source Type: Journal    
DOI: 10.1109/45.839642     Document Type: Article

References (11)

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3. Goodman, J.R., "Using Cache Memory to Reduce Processor-Memory Traffic," in Proceedings of the 10th International Symposium on Computer Architecture, 1983.
4. Handy, J., The Cache Memory Book, Second Edition, Academic Press, 1998.
5. Hennessy, J.L. and Patterson, D.A., Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, 1990.
6. Hennessy, J.L. and Patterson, D.A., Computer Architecture: A Quantitative Approach, Second Edition, Morgan Kaufmann Publishers, 1996.
7. Hwang, K., Advanced Computer Architecture: Parallelism, Scalability, Programmability, McGraw-Hill Inc., 1993.
8. Johnson, E.E., "Graffiti on 'The Memory Wall,'" ACM Computer Architecture News, Vol. 23, No. 2, 1995, pp. 7-8.
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10. Stone, H.S., High-Performance Computer Architecture, Third Edition, Addison-Wesley, 1993.
11. Wilkes, M.V., "Slave memories and dynamic storage allocation," IEEE Transactions on Electronic Computers, EC-14, No. 2, pp. 270-271, 1965.