Delay-locked loop technique for temperature stabilization of internal delays of CMOS FPGA devices

Electronics Letters

Volumn 36, Issue 14, 2000, Pages 1184-1185

  Kalisz, J ^a   Orzanowski, T ^a   Szplet, R ^a  

^a MILITARY UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; THERMODYNAMIC STABILITY;

DELAY LOCKED LOOP (DLL);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0033717514     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20000854     Document Type: Article

References (5)

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2. LJUSLIN, C., CHRISTIANSEN, J., MARCHIORE, A., and KLINGSHEIM, O.: 'An integrated 16-channel CMOS time to digital converter', IEEE Trans. Nucl. Sci., 1994, 41, (4), pp. 1104-1108
3. CHRISTIANSEN, J.: 'An integrated high resolution CMOS timing generator based on an array of delay locked loops', IEEE J. Solid-State Circuits, 1996, 31, (7), pp. 952-957
4. KALISZ, J., SZPLET, R., PELKA, R., and PONIECKI, A.: 'Single-chip interpolating time counter with 200-ps resolution and 43-s range', IEEE Trans. Instrum. Meas., 1997, 46, (4), pp. 851-856
5. PELKA, R., KALISZ, J., and SZPLET, R.: 'Nonlinearity correction of the integrated time-to-digital converter with direct coding', IEEE Trans. Instrum. Meas., 1997, 46, (2), pp. 449-453