-
1
-
-
0025566514
-
Sequential Circuit Verification Using Symbolic Model Checking
-
J. Burch E. Clarke K. McMillan D. Dill Sequential Circuit Verification Using Symbolic Model Checking Proc. 27th DAC 46 51 Proc. 27th DAC 1990
-
(1990)
, pp. 46-51
-
-
Burch, J.1
Clarke, E.2
McMillan, K.3
Dill, D.4
-
2
-
-
0028518422
-
Efficient Boolean Manipulation with OBDDs can be extended to FBDDs
-
J. Gergov C. Meinel Efficient Boolean Manipulation with OBDDs can be extended to FBDDs IEEE Trans. on Computers 43 1197 1209 1994
-
(1994)
IEEE Trans. on Computers 43
, pp. 1197-1209
-
-
Gergov, J.1
Meinel, C.2
-
3
-
-
85177120596
-
Partitioned BDDs vs. Other BDD Models
-
B. Bollig I. Wegener Partitioned BDDs vs. Other BDD Models Proc. IWLS Proc. IWLS 1997
-
(1997)
-
-
Bollig, B.1
Wegener, I.2
-
4
-
-
0022769976
-
Graph-based Algorithms for Boolean Function Manipulation
-
R. E. Bryant Graph-based Algorithms for Boolean Function Manipulation IEEE Transactions on Computers C-35 677 691 August 1986
-
(1986)
IEEE Transactions on Computers
, vol.C-35
, pp. 677-691
-
-
Bryant, R.E.1
-
5
-
-
0026913667
-
Symbolic boolean manipulation with ordered binary decision diagrams
-
R. E. Bryant Symbolic boolean manipulation with ordered binary decision diagrams ACM Computing Surveys 24 293 318 September 1992
-
(1992)
ACM Computing Surveys
, vol.24
, pp. 293-318
-
-
Bryant, R.E.1
-
6
-
-
0028736277
-
Efficient State Space Pruning in Symbolic Backward Traversal
-
G. Cabodi P. Camurati S. Quer Efficient State Space Pruning in Symbolic Backward Traversal Proc. ICCD 230 235 Proc. ICCD 1994
-
(1994)
, pp. 230-235
-
-
Cabodi, G.1
Camurati, P.2
Quer, S.3
-
7
-
-
0029474922
-
Extending Equivalence Class Computation to Large FSMs
-
G. Cabodi S. Quer P. Camurati Extending Equivalence Class Computation to Large FSMs Proc. ICCD 258 263 Proc. ICCD 1995
-
(1995)
, pp. 258-263
-
-
Cabodi, G.1
Quer, S.2
Camurati, P.3
-
8
-
-
0002684652
-
Formal VLSI Correctness Verification
-
Verification of Sequential Machines Using Boolean Functional Vectors Elsevier Sc.
-
O. Coudert C. Berthet J. Madre Formal VLSI Correctness Verification 179 196 1990 Elsevier Sc. Verification of Sequential Machines Using Boolean Functional Vectors
-
(1990)
, pp. 179-196
-
-
Coudert, O.1
Berthet, C.2
Madre, J.3
-
9
-
-
0028594117
-
Efficient representation and manipulation of switching functions based on Ordered Kronecker Functional Decision Diagrams
-
R. Drechsler Efficient representation and manipulation of switching functions based on Ordered Kronecker Functional Decision Diagrams DAC 1994
-
(1994)
DAC
-
-
Drechsler, R.1
-
10
-
-
85177106734
-
-
The University of Texas Austin
-
Y.V. Hoskote Formal Techniques for Verification of Synchronous Sequential Circuits 1995 The University of Texas Austin
-
(1995)
-
-
Hoskote, Y.V.1
-
11
-
-
0030398538
-
An ATPG-based Framework for Verifying Sequential Equivalence
-
S.-Y. Huang K.-T Cheng K.-C. Chen U. Glaeser An ATPG-based Framework for Verifying Sequential Equivalence Proc. ITC 865 874 Proc. ITC 1996
-
(1996)
, pp. 865-874
-
-
Huang, S.-Y.1
Cheng, K.-T2
Chen, K.-C.3
Glaeser, U.4
-
12
-
-
85177130719
-
Functional partitioning for verification and related problems
-
J. Jain J. Bitner D. S. Fussell J. A. Abraham Functional partitioning for verification and related problems Brown/MIT VLSI Conference Brown/MIT VLSI Conference 1992-March
-
(1992)
-
-
Jain, J.1
Bitner, J.2
Fussell, D.S.3
Abraham, J.A.4
-
13
-
-
85177120015
-
-
The University of Texas Austin
-
J. Jain On Analysis of Boolean Functions 1993 The University of Texas Austin
-
(1993)
-
-
Jain, J.1
-
15
-
-
0003830657
-
Switching and Finite Automata Theory
-
McGraw-Hill Book Company
-
Z. Kohavi Switching and Finite Automata Theory 1978 McGraw-Hill Book Company
-
(1978)
-
-
Kohavi, Z.1
-
17
-
-
85177134679
-
Partitioned-ROBDDs - A Compact, Canonical and Efficiently Manipulable Representation for Boolean Functions
-
A. Narayan J. Jain M. Fujita A. L. Sangiovanni-Vincentelli Partitioned-ROBDDs-A Compact, Canonical and Efficiently Manipulable Representation for Boolean Functions ICCAD ICCAD 1996-November
-
(1996)
-
-
Narayan, A.1
Jain, J.2
Fujita, M.3
Sangiovanni-Vincentelli, A.L.4
-
19
-
-
0000318151
-
A Theory and Implementation of Sequential Hardware Equivalence
-
C. Pixley A Theory and Implementation of Sequential Hardware Equivalence IEEE Trans. on CAD 1469 1494 1992
-
(1992)
IEEE Trans. on CAD
, pp. 1469-1494
-
-
Pixley, C.1
-
20
-
-
0028728362
-
Multi-level Synthesis for Safe Replaceability
-
C. Pixley V. Singhal A. Aziz R. K. Brayton Multi-level Synthesis for Safe Replaceability Proc. ICCAD 442 449 Proc. ICCAD 1994
-
(1994)
, pp. 442-449
-
-
Pixley, C.1
Singhal, V.2
Aziz, A.3
Brayton, R.K.4
-
22
-
-
0003046983
-
NC-Algorithms for Operations on Binary Decision Diagrams
-
D. Sieling I. Wegener NC-Algorithms for Operations on Binary Decision Diagrams Parallel Processing Letters 3 3 12 1993
-
(1993)
Parallel Processing Letters
, vol.3
, pp. 3-12
-
-
Sieling, D.1
Wegener, I.2
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