DSP implementation issues for UMTS-channel coding

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 6, Issue , 2000, Pages 3219-3222

  Walther, U ^a   Fettweis, G P ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL CODING; COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; DIGITAL SIGNAL PROCESSORS; NETWORK ARCHITECTURE; WIRELESS TELECOMMUNICATION SYSTEMS; ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); CONVOLUTION; DATA TRANSFER; DECODING; ENCODING (SYMBOLS); MAXIMUM LIKELIHOOD ESTIMATION; MOBILE TELECOMMUNICATION SYSTEMS; PROBABILITY; VECTORS;

CHANNEL CODING SCHEMES; DIGITAL SIGNAL PROCESSOR DEVICES; DSP IMPLEMENTATION; DUAL MODES; PROCESSOR ARCHITECTURES; WIRELESS COMMUNICATION STANDARDS;

SIGNAL PROCESSING; DIGITAL SIGNAL PROCESSING;

CHANNEL CODING; DATAPATH; MAXIMUM A POSTERIORI; MEMORY INTERFACE DESIGN; VITERBI ALGORITHM;

EID: 0033709660     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.2000.860085     Document Type: Conference Paper

References (8)

1. J. Vogt, K. Koora, A. Finger, and G. Fettweis, "Comparison of different Turbo Decoder Realizations for IMT2000", accepted GLOBECOM'99, 1999.
2. G. Fettweis, "DSP Cores for Mobile Communications: Where are we going?", in Proc. ICASSP'97, pp. 279-282.
3. G. Fettweis et al., "Breaking new grounds over 3000M MAC/s", in Proc. ICSPAT'98, vol. II, pp. 543-547.
4. M. Weiss and G. Fettweis, "Dynamic Codewidth Reduction for VLIW Instruction Set Architectures in Digital Signal Processors", in Proc. IWJSP'96, 1996, pp. 517-520.
5. C. Berrou and A. Glavieux, "Near optimum error correcting coding and decoding: Turbo codes", IEEE Trans. Com., vol. 44, no. 10, pp. 1261-1271, Oct. 1996.
6. L. Bahl, J. Cocke, F. Jelinek, and J. Raviv, "Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate", IEEE Trans. IT, pp. 284-287, Mar. 1974.
7. O. M. Collins, "The Subtleties and Intricacies of Building a Constraint Length 15 Convolutional Decoder", IEEE Trans. Com., vol. 40, no. 12, pp. 1810-1819, Dec. 1992.
8. H. Dawid H. Meyer, "Real-Time Algorithms and VLSI Architectures for Soft Output MAP Convoltional Decoding", in Proc. 6th PIMRC, 1996, vol. 1, pp. 193-197.