Cacheminer: a runtime approach to exploit cache locality on SMP

IEEE Transactions on Parallel and Distributed Systems

Volumn 11, Issue 4, 2000, Pages 357-374

  Yan, Yong ^a,b   Zhang, Xiaodong ^a,c   Zhang, Zhao ^a,c  

^a IEEE   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

^c The College of William and Mary   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE LOCALITY; CACHEMINER SYSTEM; DYNAMIC MEMORY ACCESS PATTERNS; NESTED LOOPS; RUNTIME SYSTEMS; SYMMETRIC MULTIPROCESSOR SYSTEMS; TASK SCHEDULING;

BUFFER STORAGE; C (PROGRAMMING LANGUAGE); CLIENT SERVER COMPUTER SYSTEMS; COMPUTER SIMULATION; DYNAMIC RANDOM ACCESS STORAGE; INTERCONNECTION NETWORKS; INTERFACES (COMPUTER); OPTIMIZATION; PARALLEL ALGORITHMS; PROGRAM COMPILERS; RESPONSE TIME (COMPUTER SYSTEMS);

PARALLEL PROCESSING SYSTEMS;

EID: 0033703258     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/71.850833     Document Type: Article

References (26)

1. J.M. Anderson, S.P. Amarasinghe, and M.S. Lam, "Data and Computation Transformations for Multiprocessors," Proc. Fifth ACM SIGPLAN Symp. Principles and Practice of Parallel Programming, pp. 166-178, July 1995.
2. J.M. Anderson and M.S. Lam, "Global Optimizations for Parallelism and Locality on Scalable Parallel Machines," Proc. ACM SIGPLAN'93 Conf. Programming Language Design and Implementation, pp. 112-125, June 1993.
3. G. Astfalk and T. Brewer, "An Overview of the HP/Convex Exemplar Hardware," technical report, Hewlett-Packard, Mar. 1997.
4. R. Chandra, A. Gupta, and J.L. Hennessy, "Data Locality and Load Balancing in COOL," Proc. ACM SIGPLAN Symp. Principles and Practice of Parallel Programming, pp. 249-259, May 1993.
5. A. Charlesworth, N. Aneshansley, M. Haakmeester, D. Drogichen, G. Gilbert, R. Williams, and A. Phelps, "The Startfire SMP Interconnect," Proc. Supercomputing '97, Nov. 1997.
6. S. Coleman and K.S. McKinley, "Tile Size Selection Using Cache Organization and Data Layout," Proc. SIGPLAN '95 Conf. Programming Language Design and Implementation, pp. 279-289, June 1995.
7. M. Galles and E. Williams, "Performance Optimizations, Implementation, and Verification of the SGI Challenge Multiprocessor," Proc. 27th Hawaii Int'l Conf. System Sciences, vol. 1, pp. 134-143, Jan. 1994.
8. T.E. Jeremiassen and S.J. Eggers, "Reducing False Sharing on Shared Memory Multiprocessors through Compile Time Data Transformations," Proc. Fifth ACM SIGPLAN Symp. Principles and Practice of Parallel Programming, pp. 179-188, July 1995.
9. I. Kodukula, N. Ahmed, and K. Pingali, "Data-Centric Multi-Level Blocking," Proc. ACM SIGPLAN Conf. Programming Language Design and Implementation, pp. 346-357, May 1997.
10. A.R. Lebeck and D.A. Wood, "Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors," Proc. 22nd Annual Int'l Symp. Computer Architecture, pp. 48-59, 1995.
11. M.S. Lam, E.E. Rothberg, and M.E. Wolf, "The Cache Performance and Optimizations of Blocked Algorithms," Proc. ASPLOS '91, pp. 63-74, Apr. 1991.
12. H. Li, S. Tandri, M. Stumm, and K.C. Sevcik, "Locality and Loop Scheduling on NUMA Multiprocessors," Int'l Conf. Parallel Processing vol. II, pp. 140-144, 1993.
13. E.P. Markatos and T.J. LeBlanc, "Using Processor Affinity in Loop Scheduling Scheme on Shared-Memory Multiprocessors," IEEE Trans. Parallel and Distributed Systems, vol. 5, no. 4, pp. 379-400, Apr. 1994.
14. K.S. McKinley, S. Carr, and C.W. Tseng, "Improving Data Locality with Loop Transformations," ACM Trans. Programming Languages and Systems, vol. 18, no. 4, pp. 424-453, July 1996.
15. K.S. McKinley and O. Teman, "A Quantitative Analysis of Loop Nest Locality," Proc. ASPLOS '96, pp. 94-104, Oct. 1996.
16. J. Philbin, J. Edler, O.J. Anshus, C.C. Douglas, and K. Li, "Thread Scheduling for Cache Locality," Proc. ASPLOS '96, pp. 60-71, Oct. 1996.
17. C. Polychronopoulos and D. Kuck, "Guided Self-Scheduling: A Practical Self-Scheduling Scheme for Parallel Supercomputers," IEEE Trans. Computers, vol. 36, no. 12, pp. 1,425-1,439, Dec. 1987.
18. M. Rosenblum, E. Bugnion, S. Devine, and S.A. Herrod, "Using the SimOS Machine Simulator to Study Complex Computer Systems," ACM Trans. Modeling and Computer Simulation, vol. 7, no. 1, pp. 78-103, 1997.
19. M.B. Steinman, G.J. Harris, A. Kocev, V.C. Lamere, and R.D. Pannell, "The AlphaServer 4100 Cached Processor Module Architecture and Design," Digital Technical J. vol. 8, no. 4, pp. 21-37, 1996.
20. J. Torrellas, M.S. Lam, and J.L. Hennessy, "False Sharing and Spatial Locality in Multiprocessor Caches," IEEE Trans. Computers, vol. 43, no. 6, pp. 651-663, June 1994.
21. J.E. Veenstra and R.J. Fowler, "MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors," Proc. MASCOTS '94, pp. 201-207, Jan. 1994.
22. M. Wolfe, High Performance Compilers For Parallel Computing. Addison-Wesley, 1996.
23. M.E. Wolf and M. Lam, "A Data Locality Optimizing Algorithm," Proc. ACM SIGPLAN '91 Conf. Programming Language Design and Implementation, pp. 30-44, June 1991.
24. Y. Yan, "Exploiting Cache Locality on Symmetric Multiprocessors: A Run-Time Approach," PhD dissertation, Dept. Computer Science, College of William and Mary, June 1998.
25. Y. Yan, C.M. Jin, and X. Zhang, "Adaptively Scheduling Parallel Loops in Distributed Shared-Memory Systems," IEEE Trans. Parallel and Distributed Systems, vol. 8, no. 1, pp. 70-81, Jan. 1997.
26. Y. Yan, X. Zhang, and Z. Zhang, "A Memory-Layout Oriented Runtime Technique for Locality Optimization," Proc. 1998 Int'l Conf. Parallel Processing (ICPP '98), pp. 189-196, Aug. 1998.