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Volumn 1, Issue , 2000, Pages I-8-I-11

From nanotechnology to nanoelectronic systems, from SETs to neural nets

Author keywords

[No Author keywords available]

Indexed keywords


EID: 0033684693     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2000.856405     Document Type: Article
Times cited : (6)

References (15)
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    • 0031099652 scopus 로고    scopus 로고
    • Embedded Software in Real-Time Signal Processing Systems: Application and Architecture Trends
    • P. Paulin C. Liem M. Cornero F. Naçabal G. Goossens Embedded Software in Real-Time Signal Processing Systems: Application and Architecture Trends Proc. of the IEEE 85 3 419 435 March 1997
    • (1997) Proc. of the IEEE , vol.85 , Issue.3 , pp. 419-435
    • Paulin, P.1    Liem, C.2    Cornero, M.3    Naçabal, F.4    Goossens, G.5
  • 2
    • 85052581097 scopus 로고    scopus 로고
    • Managing Power-Dissipation in the Generation-after-Next Wireless Systems
    • J. M. Rabaey Managing Power-Dissipation in the Generation-after-Next Wireless Systems FTFC'99 FTFC'99 Paris France 1999
    • (1999)
    • Rabaey, J.M.1
  • 4
    • 85177131731 scopus 로고    scopus 로고
    • Instruction-set Modelling for ASIP Code Generation
    • R. Leupers P. Marwedel Instruction-set Modelling for ASIP Code Generation 9th Int. Conf. on VLSI Design 9th Int. Conf. on VLSI Design 1996-January
    • (1996)
    • Leupers, R.1    Marwedel, P.2
  • 6
    • 85177113245 scopus 로고    scopus 로고
    • Hardware Module Selection for Real-Time Pipeline Architectures using Probabilistic Cost Estimation
    • NY
    • O. Sentieys J. P. Diguet J. L. Philippe E. Martin Hardware Module Selection for Real-Time Pipeline Architectures using Probabilistic Cost Estimation IEEE Int. ASIC Conf. IEEE Int. ASIC Conf. Rochester USA NY 1996-September
    • (1996)
    • Sentieys, O.1    Diguet, J.P.2    Philippe, J.L.3    Martin, E.4
  • 7
    • 85177117757 scopus 로고    scopus 로고
    • Area-Time-Power Space Exploration in Module Selection for DSP High Level Synthesis
    • S. Gailhard O. Sentieys N. Julien E. Martin Area-Time-Power Space Exploration in Module Selection for DSP High Level Synthesis PATMOS'97 PATMOS'97 Louvain-la-Neuve 1997-September
    • (1997)
    • Gailhard, S.1    Sentieys, O.2    Julien, N.3    Martin, E.4
  • 8
    • 85177134477 scopus 로고    scopus 로고
    • ASIP Design and Power Estimation for DSP Applications
    • J-G. Cousin D. Chillet O. Sentieys ASIP Design and Power Estimation for DSP Applications SAME'98, Conf. on MicroElectronics SAME'98, Conf. on MicroElectronics Sophia-Antipolis 1998-October
    • (1998)
    • Cousin, J-G.1    Chillet, D.2    Sentieys, O.3
  • 9
    • 85177141373 scopus 로고
    • Power Profiler: Optimizing ASICs Power Consumption at the Behavioral Level
    • R. S. Martin J. P. Knight Power Profiler: Optimizing ASICs Power Consumption at the Behavioral Level 32nd Design Automation Conference 32nd Design Automation Conference San Francisco 1995
    • (1995)
    • Martin, R.S.1    Knight, J.P.2
  • 10
    • 85177142714 scopus 로고    scopus 로고
    • Memory Module Selection for High Level Synthesis
    • O. Sentieys D. Chillet J-P. Diguet J-L. Philippe Memory Module Selection for High Level Synthesis IEEE Workshop on VLSI Signal Processing IEEE Workshop on VLSI Signal Processing San-Francisco 1996-October
    • (1996)
    • Sentieys, O.1    Chillet, D.2    Diguet, J-P.3    Philippe, J-L.4
  • 11
    • 0002774808 scopus 로고
    • Behavorial Level Power Estimation and Exploration
    • R. Mehra J. M. Rabaey Behavorial Level Power Estimation and Exploration Proc. first Int. Workshop on Low-Power Design 197 202 Proc. first Int. Workshop on Low-Power Design Napa Valley 1994-April
    • (1994) , pp. 197-202
    • Mehra, R.1    Rabaey, J.M.2
  • 12
    • 0003113577 scopus 로고
    • Black-Box Capacitance Models for Architectural Power Analysis
    • P. E. Landman J. M. Rabaey Black-Box Capacitance Models for Architectural Power Analysis Proc. of Int. Workshop on Low-Power Design Proc. of Int. Workshop on Low-Power Design 1994-April
    • (1994)
    • Landman, P.E.1    Rabaey, J.M.2
  • 13
    • 85177130419 scopus 로고    scopus 로고
  • 15
    • 85177143374 scopus 로고    scopus 로고
    • PowerCheck: un outil d'estimation de la consommation au niveau architectural
    • D. Saillé M. Denoual J-G. Cousin O. Sentieys PowerCheck: un outil d'estimation de la consommation au niveau architectural FTFC'99 FTFC'99 Paris France 1999-mai
    • (1999)
    • Saillé, D.1    Denoual, M.2    Cousin, J-G.3    Sentieys, O.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.