Subsetting behavioral intellectual property for low power ASIP design

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 21, Issue 3, 1999, Pages 209-218

  Dougherty, William E ^a   Pursley, David J ^a   Thomas, Donald E ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SOFTWARE; INTELLECTUAL PROPERTY; MICROPROCESSOR CHIPS; PROGRAM COMPILERS; SIMULATORS;

APPLICATION SPECIFIC INSTRUCTION SET PROCESSOR; HARDWARE SOFTWARE CODESIGN; INSTRUCTION SUBSETTING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0032663984     PISSN: 09225773     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008010602067     Document Type: Article

References (20)

1. H. Ing-Jer and A.M. Despain, "Generating instruction sets and microarchitectures from applications," International Conference on Computer-Aided Design, pp. 391-396, Nov. 1994.
2. A. Raghunathan and N.K. Jha, "Behavioral synthesis for low power," International Conference on Computer-Aided Design, pp. 318-322, Oct. 1994.
3. R. Mehra and J. Rabaey, "Exploiting regularity for low-power design," International Conference on Computer-Aided Design, pp. 166-172, Nov. 1996.
4. F. Catthoor, L. Nachtergaele, and S. Wuytack, "Optimizing data transfers and memory for low power," ASIC & EDA Magazine, Spring 1997.
5. V. Tiwari, S. Malik, and A. Wolfe, "Compilation techniques for low energy: An overview," International Symposium on Low-Power Electronics, pp. 38-39, Oct. 1994.
6. M. Srivastava and M. Potkonjak, "Power optimization in programmable processors and ASIC implementations of linear systems: Transformation-based approach," Design Automation Conference, pp. 434-348, June 1996.
7. J. Monteiro, S. Devadas, P. Ashar, and A. Mauskar, "Scheduling techniques to enable power management," Design Automation Conference, pp. 349-356, June 1996.
8. P. Paulin, C. Liem, T. May, and S. Sutarwala, "DSP design tool requirements for embedded systems: A telecommunications industrial perspective," Journal of VLSI Signal Processing, pp. 23-47, Jan. 1995.
9. M68HC11 Reference Manual, Motorola, 1991.
10. DSP56000/56001 digital signal processor user's manual, Motorola, 1990.
11. R. Williams, "fft.c11 - fast fourier transform for the MC68HC-11," http://www.mcu.motsps.com/freeweb/pub/mcu11/ffthc11. asm, March, 1994.
12. Archive Containing DSP56000-related files, Motorola, http:// www.mot.com/pub/SPS/DSP/software/dr.bub/56000.zip, Jan. 1992.
13. N. Weinberg, private communication.
14. Rapid Package User's Manual, Dasys, Oct. 1997.
15. DesignWare User Guide, Synopsys, Aug. 1997.
16. "Cascade design automation corporation," Epoch User's Manual, Feb. 1997.
17. D.J. Pursley, "A gate level simulator for power consumption analysis," M.S. thesis, Carnegie Mellon University, May 1996.
18. S. Coumeri and D. Thomas, "Memory modeling for system synthesis," International Symposium on Low Power Electronics and Design, pp. 179-184, Aug. 1998.
19. M. Horowitz, T. Indermaur, and R. Gonzalez, "Low power digital design," International Symposium on Low Power Electronics, pp. 8-11, Oct. 1994.
20. B. Klass et al., "Modeling inter-instruction energy effects in a digital signal processor," Power Driven Microarchitecture Workshop ISCA98, pp. 25-30, June 1998.