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Volumn 4, Issue , 2000, Pages IV-9-IV-12

Performance of submicron CMOS devices and gates with substrate biasing

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; LEAKAGE CURRENTS; SUBSTRATES;

EID: 0033682308     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2000.858675     Document Type: Article
Times cited : (17)

References (12)
  • 1
    • 0028745562 scopus 로고
    • A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-low Voltage Operation
    • F. Assaderaghi A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-low Voltage Operation IEDM Tech. Dig 809 812 IEDM Tech. Dig 1994
    • (1994) , pp. 809-812
    • Assaderaghi, F.1
  • 2
    • 0032049972 scopus 로고    scopus 로고
    • Back-gate bias enhanced bend-to-band tunneling leakage in scaled MOSFET's
    • M.-J. Chen Back-gate bias enhanced bend-to-band tunneling leakage in scaled MOSFET's IEEE Electron Device Letters 19 4 134 136 1998
    • (1998) IEEE Electron Device Letters , vol.19 , Issue.4 , pp. 134-136
    • Chen, M.-J.1
  • 3
    • 0030146154 scopus 로고    scopus 로고
    • Power dissipation analysis and optimization of deep submicron CMOS digital circuits
    • R. X. Gu M. I. Elmasry Power dissipation analysis and optimization of deep submicron CMOS digital circuits IEEE Journal of Solid-State Circuits 31 5 707 713 1996
    • (1996) IEEE Journal of Solid-State Circuits , vol.31 , Issue.5 , pp. 707-713
    • Gu, R.X.1    Elmasry, M.I.2
  • 4
    • 85177143299 scopus 로고    scopus 로고
    • Novel Bulk Dynamic Threshold Voltage MOSFET (B-DMOS) with Advanced Isolation (SITOS) and Gate to Shallow-Well Contact (SSS-C) Processes for Ultra Low Power Dual Gate CMOS
    • H. Kotaki Novel Bulk Dynamic Threshold Voltage MOSFET (B-DMOS) with Advanced Isolation (SITOS) and Gate to Shallow-Well Contact (SSS-C) Processes for Ultra Low Power Dual Gate CMOS IEDM Tech. Dig. 459 461 IEDM Tech. Dig. 1996
    • (1996) , pp. 459-461
    • Kotaki, H.1
  • 5
    • 85177111934 scopus 로고    scopus 로고
    • Evaluation of body Biasing Engineering on performance of scaled CMOS devices
    • M. Liu S. Mourad Evaluation of body Biasing Engineering on performance of scaled CMOS devices Proc. SPIE Symposium on Solid State Technology 138 145 Proc. SPIE Symposium on Solid State Technology 1999
    • (1999) , pp. 138-145
    • Liu, M.1    Mourad, S.2
  • 6
    • 0027187367 scopus 로고
    • Threshold voltage model for deep-submicrometer MOSFET's
    • Z.-H. Liu Threshold voltage model for deep-submicrometer MOSFET's IEEE Trans. on Electron Devices 40 1 86 94 1993
    • (1993) IEEE Trans. on Electron Devices , vol.40 , Issue.1 , pp. 86-94
    • Liu, Z.-H.1
  • 8
    • 85177110044 scopus 로고    scopus 로고
    • A Sub-0.1 um Circuit Design with Substrate-over-Biasing
    • Y. Oowaki A Sub-0.1 um Circuit Design with Substrate-over-Biasing Proceedings of ISSCC98 88 89 Proceedings of ISSCC98 1998
    • (1998) , pp. 88-89
    • Oowaki, Y.1
  • 9
    • 0029253931 scopus 로고
    • 50% Active-Power Saving without Speed Degradation using Standby Power Reduction (SPR) Circuit
    • K. Seta 50% Active-Power Saving without Speed Degradation using Standby Power Reduction (SPR) Circuit ISSCC95, Tech. Dig 318 319 ISSCC95, Tech. Dig 1995
    • (1995) , pp. 318-319
    • Seta, K.1
  • 10
    • 85177114333 scopus 로고    scopus 로고
    • Ultra Low Power Supply Voltage (0.3V) Operation with Extreme High Speed Using Bulk Dynamic Threshold Voltage MOSFET (B-DTMOS) with Advanced Fast-Signal-Transmission Shallow Well
    • A. Shibata Ultra Low Power Supply Voltage (0.3V) Operation with Extreme High Speed Using Bulk Dynamic Threshold Voltage MOSFET (B-DTMOS) with Advanced Fast-Signal-Transmission Shallow Well Symposium on VLSI Technology Digest of Technical Papers Symposium on VLSI Technology Digest of Technical Papers 1998
    • (1998)
    • Shibata, A.1
  • 11
    • 85177137272 scopus 로고    scopus 로고
    • Dual Threshold Voltage and Substrate Bias: Keys to High Performance, Low Power, 0.1 μm Logic Design
    • S. Thomapson Dual Threshold Voltage and Substrate Bias: Keys to High Performance, Low Power, 0.1 μm Logic Design Symposium on VLSI Technology Digest of Technical Papers Symposium on VLSI Technology Digest of Technical Papers 1997
    • (1997)
    • Thomapson, S.1
  • 12
    • 0016113965 scopus 로고
    • A Simple Theory to Predict the Threshold Voltage of Short-Channel IGFET's
    • L. D. Yau A Simple Theory to Predict the Threshold Voltage of Short-Channel IGFET's Solid State Electronics 17 1059 1063 1974
    • (1974) Solid State Electronics , vol.17 , pp. 1059-1063
    • Yau, L.D.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.