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Volumn , Issue , 1999, Pages 123-133

Improving simulation accuracy in design methodologies for dynamically reconfigurable logic systems

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; MATHEMATICAL MODELS; OPTIMIZATION;

EID: 0033488494     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (6)

References (14)
  • 1
    • 0012175175 scopus 로고
    • VHDL initiative toward ASIC libraries (VITAL) model development specification
    • Mar. 25; Version 2.2b
    • VHDL Initiative Toward ASIC Libraries (VITAL) Model Development Specification. ftp://vhdl.org/pub/vital/Spec/v2.2b/, Mar. 25 1994. Version 2.2b.
    • (1994)
  • 6
    • 19944410750 scopus 로고
    • IEEE standard multivalue logic system for VHDL model interoperability (Std_logic_1164)
    • IEEE.; May 26
    • IEEE. IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164), May 26 1993.
    • (1993)
  • 7
    • 0030414980 scopus 로고    scopus 로고
    • Modelling and optimising run-time reconfigurable systems
    • W. Luk, N. Shirazi, and P. Y. K. Cheung. Modelling and optimising run-time reconfigurable systems. In FCCM '96 [3], pages 167-176.
    • FCCM '96 [3] , pp. 167-176
    • Luk, W.1    Shirazi, N.2    Cheung, P.Y.K.3
  • 9
    • 0030242765 scopus 로고    scopus 로고
    • A simulation tool for dynamically reconfigurable field programmable gate arrays
    • Sept.
    • P. Lysaght and J. Stockwood. A simulation tool for dynamically reconfigurable field programmable gate arrays. IEEE Transactions on VLSI Systems, 4(3):381-390, Sept. 1996.
    • (1996) IEEE Transactions on VLSI Systems , vol.4 , Issue.3 , pp. 381-390
    • Lysaght, P.1    Stockwood, J.2
  • 11
    • 85088329872 scopus 로고    scopus 로고
    • Expressing dynamic reconfiguration by partial evaluation
    • S. Singh, J. Hogg, and D. McAuley. Expressing dynamic reconfiguration by partial evaluation. In FCCM '96 [3].
    • FCCM '96 [3]
    • Singh, S.1    Hogg, J.2    McAuley, D.3
  • 13
    • 0003874879 scopus 로고    scopus 로고
    • XC6200 field programmable gate arrays
    • Xilinx.; Xilinx, Inc., Apr.; Advanced Product Information, Version 1.10
    • Xilinx. XC6200 Field Programmable Gate Arrays. Xilinx, Inc., Apr. 1997. Advanced Product Information, Version 1.10.
    • (1997)
  • 14
    • 0003465787 scopus 로고    scopus 로고
    • XACTstep Series 6000 User Guide
    • Xilinx, Inc.
    • Xilinx, Inc. XACTstep Series 6000 User Guide, 1997.
    • (1997)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.