ESD production for deep submicron triple well CMOS technologies

Electronics Letters

Volumn 35, Issue 23, 1999, Pages 2025-2028

  Nikolaidis, T ^a   Papadas, C ^b  

^a Integrated Systems Development SA   (Greece)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC BREAKDOWN; ELECTRIC DISCHARGES; ELECTRIC POTENTIAL; GATES (TRANSISTOR); MOSFET DEVICES; SEMICONDUCTOR QUANTUM WELLS;

GATE OXIDE RELIABILITY; PROTECTION TRANSISTOR;

CMOS INTEGRATED CIRCUITS;

EID: 0033352721     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19991393     Document Type: Article

References (4)

1. DUVVURY, C., and AMERASEKERA, A.: 'ESD: a pervasive reliability concern for IC technologies', Proc. IEEE, 1993, 81, (5), pp. 690-702
2. HUH, Y., LEE, M.G., LEE, J., JUNK, H.C., LI, T., SONG, H., LEE, Y.J., HWANG, J.M., SUNG, Y.K., and KANG, S.K.: 'A study of ESD-induced latent damage in CMOS integrated circuits', Proc. IRPS, 1998, 36, pp. 279-283
3. DUVVRY, C., and DIAZ, C.: 'Dynamic gate coupling of NMOS for efficient output ESD protection', Proc. IRPS, 1992, 30, pp. 141-150
4. AMERASEKERA, A., DUVURY, C., REDDY, Y., and RODDER, M.: 'Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes'. Proc. IEDM Tech. Dig., 1995, pp. 547-550