Redundancy management in arithmetic processing via redundant binary representations

Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers

Volumn 2, Issue , 1999, Pages 1475-1479

  Phatak, D S ^a   Goff, T ^a   Koren, I ^b  

^a State University of New York   (United States)

^b University of Massachusetts   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY REPRESENTATIONS; COMPREHENSIVE ANALYSIS; COMPUTER ARITHMETIC; CONSTANT TIME; DIGIT SET; FORMAT CONVERSION; REDUNDANCY MANAGEMENT; REDUNDANT REPRESENTATION;

BINS; DIGITAL ARITHMETIC;

COMPUTATION THEORY; REDUNDANCY;

REDUNDANCY MANAGEMENT; REDUNDANT BINARY REPRESENTATIONS;

EID: 0033345976     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSSC.1999.831995     Document Type: Conference Paper

References (9)

1. J P. Kornerup, "Necessary and Sufficient Conditions for Parallel and Constant Time Conversion and Addition, " in Proc. 14th IEEE Symposium on Computer Arithmetic, pp. 152-156, IEEE Computer Society, April 1999.
2. P. Kornerup, "Digit-Set Conversions: Generalizations and Applications, " IEEE Transactions on Computers. vol. C-43, pp. 622-629, May 1994.
3. B. Parhami, "Generalized signed-digit number systems: A unifying framework for redundant number representations, " IEEE Transactions on Computers, vol. C-39, pp. 89-98, Jan. 1990.
4. C. Nagendra, R. M. Owens, and M. J. Irwin, "Unifying Carry-Sum and Signed-Digit Number Representations, " Tech. Rep. CSE-96-036, Computer Science and Engineering Department, Pennsylvania State University, 1996.
5. D. S. Phatak and 1. Koren, "Hybrid Signed-Digit Number Systems: A Unified Framework for Redundant Number Representations with Bounded Carry Propagation Chains, " IEEE Trans. on Computers, vol. TC-43, pp. 880-891, Aug. 1994.
6. J. J. J. Lue and D. S. Phatak, "Area x Delay (A. T ) Efficient Multiplier Based on an Intermediate Hybrid Signed-Digit (HSD-1) Representation, " Proc. of the 14th IEEE International Symposium on Computer Arithmetic, pp. 216-224, April 1999.
7. D. S. Phatak, T. Goff and I. Koren, "On Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations, " IEEE Transactions on Computers, submitted.
8. S. Kuninobu, T. Nishiyama, H. Edamatsu, T. Taniguchi, and N. Takagi, "Design of high speed MOS multiplier and divider using redundant binary representation, " Proc. of the 8th Symposium on Computer Arithmetic, pp. 80-86, 1987.
9. N. Ohkubo and Suzuki, M., et. al., "A 4.4-11s CMOS 54 x 54-b Multiplier Using Pass-Transistor Multiplexor, " IEEE Journal of Solid-state Circuits, vol. 30, pp. 251-256, Mar. 1995.