Application of a resource planning system for a VLSI assembly facility

1999 IEEE International Symposium on Semiconductor Manufacturing, ISSM 1999 - Conference Proceedings

Volumn , Issue , 1999, Pages 345-348

  Saito, K ^a   Arima, S ^a   Yokoyama, T ^b   Yamanaka, H ^b  

^a Fujitsu Tohoku Elec Ltd   (Japan)

^b UNIVERSITY OF AIZU   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

MACHINERY; MANUFACTURE; QUEUEING THEORY; RESOURCE ALLOCATION; SEMICONDUCTOR DEVICE MANUFACTURE; TURNAROUND TIME; ALGORITHMS; PLANNING; SEMICONDUCTOR DEVICE MODELS; VLSI CIRCUITS;

CALCULATION TIME; PLANNING SYSTEMS; QUEUEING MODEL; REAL APPLICATIONS; RESOURCE PLANNING SYSTEM;

VLSI CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE;

M/M/M QUEUEING MODELS;

EID: 0033334812     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSM.1999.808807     Document Type: Conference Paper

References (4)

1. R, Uzsoy, J. A. Martin-Vega, C.-Y. Lee, and P. A. I. Conard, Prod LieU on schedul i rig algorm t uris for a semiconductor test facility, " JEEJZ Trans. Senrico, tduetor Manufacturing, vol. 4, no. 4, pp. 270-280, Nov. 1991
2. K. Saito, "Optimization of the number of Machines and Operators Required for 1. 51 Production, " IEEE Trans. , P79 C, pp. 1112-1119(1996).
3. T. Altiok, "Perfarnionee Analysis of Manufacturing Sysreni, " Springer-Verlag New York, 1997.
4. L. Kleinleck, "Queueing Systcosr Vol. 1, " John Wiley, 1975.