Optimization of the numbers of machines and operators required for LSI production

IEICE Transactions on Electronics

Volumn E79-C, Issue 8, 1996, Pages 1112-1119

  Saito, Kazuyuki ^a  

^a UNIVERSITY OF AIZU   (Japan)

Author keywords

Facility design; Integrated electronics; Manufacturing system; Queueing model; VLSI

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC MACHINERY; ESTIMATION; FABRICATION; INTEGRATED CIRCUIT MANUFACTURE; MATHEMATICAL MODELS; QUEUEING THEORY; SYSTEMS ANALYSIS; VLSI CIRCUITS;

BATCH PROCESSING; CONTINUOUS PROCESSING; INTEGRATED ELECTRONICS;

LSI CIRCUITS;

EID: 0030219421     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (6)

1. E. Arai, S. Nakamura, T. Sakurai, and A. Kojima, "Configuration of a manufacturing line for mixed production of ultra-short TAT LSIs and low-cost LSIs," IEICE Trans. Electron., vol. E78-C, no. 3, pp. 214-221, March 1995.
2. R. Uzsoy, L. A. Martin-Vega, C.-Y. Lee, and P. A. Leonard, "Production scheduling algorithms for a semiconductor test facility," IEEE Trans. Semiconductor Manufacturing, vol.4, no. 4, pp. 270-280, Nov. 1991.
3. C. Hashimoto, T. Takeda, S. Tazawa, and T. Sakurai, "Practical scheduling and line optimization technology for ASIC manufacturing lines," IEEE Trans. Components, Hybrids, and Manufacturing Technology, vol. 16, no. 4, pp. 407-411, June 1993.
4. L. Kleinrock, "Queueing Systems Vol. 1: Theory," John Wiley, New York, 1975.
5. K. Lynes and J. Mitenberg, "The application of an open queueing network to the analysis of cycle time, variability, throughput, inventory and cost in the batch production system of a microelectronics manufacturer," Int. J. Production Economics, vol. 37, pp. 189-203, 1994.
6. "Report on Large Sized Wafer Technology," vol. 90-ki-22, Japan Electronic Industry Development Association (JEIDA), March 1990.