Optimized sample planning for wafer defect inspection

1999 IEEE International Symposium on Semiconductor Manufacturing, ISSM 1999 - Conference Proceedings

Volumn , Issue , 1999, Pages 43-46

  Williams, R ^a   Gudmundsson, D ^b   Monahan, K ^b   Shanthikumar, J G ^c  

^a INTEL CORPORATION   (United States)

^b KLA TENCOR CORPORATION   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COSTS; DEFECTS; MANUFACTURE; SEMICONDUCTOR DEVICE MANUFACTURE; CRYSTAL DEFECTS; INDUSTRIAL ELECTRONICS; INSPECTION; LIFE CYCLE; MARKETING; PROCESS ENGINEERING; PRODUCT DEVELOPMENT; SILICON WAFERS;

BUSINESS ENVIRONMENTS; DEFECT INSPECTION; FAB CONSTRUCTION; OPERATIONAL PHASE; PROCESS TECHNOLOGIES; PRODUCT LIFE CYCLES; SEMICONDUCTOR MANUFACTURERS; SEMICONDUCTOR MANUFACTURING LINE;

LIFE CYCLE; SEMICONDUCTOR DEVICE MANUFACTURE;

WAFER DEFECT INSPECTION;

EID: 0033333765     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSM.1999.808734     Document Type: Conference Paper

References (4)

1. Nurani, R. K . Akella, R. , Slrojwas, A. J. "Ill-line Deject Sampling Methodology in Yield Management: An Integrated Framework ". IEEE Transactions on Semiconductor Manufacturing. Vol. 9, No. 4, November 1996
2. Williams, K K. , Nitrani, it K. Sampling Plan flpnOiicaunii 101 a Multi Product Scennno ii Semiconductor Manufacturing . K/A Tencor Yield Management Sections. SCM iCON/West, July 15. 1937
3. Nurani, K K. , . Sioller, S. , Ciudinundsaon, O , and Sheistsikumar, U "Isaluanng inspection Strategies Using Advanced Ste neural Methods ". KL. A-Tcneoi Yield Managerneni Solatiorss, Vol I, Issue 3, Spring 1999, p 12-14
4. Williams, R. R. . Oudniuadsson, D. , Noun, R. K. , Sioller. M. , Cliaiierjee, A , Sesliadri, S , Shanthikumar, . 1 0. Challenging shc Paradigm of Monitor Ilerluction to Achieve Loner Product (5, n )llse 10th Annual IEEE/SEMI Advanced Scmicondtietn, Manufacturing Conference and Workshop, Sepicmber 5 10, 1999