An investigation on power plane decoupling for high speed multiprocessor boards

IEEE International Symposium on Electromagnetic Compatibility

Volumn 1, Issue , 1999, Pages 355-360

  Nuebel, Joe ^a   Roy, Tanmoy ^a   Das, Sudip ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; COMPUTER SIMULATION; ELECTRIC IMPEDANCE; FAST FOURIER TRANSFORMS; HORN ANTENNAS; NATURAL FREQUENCIES; OPTIMIZATION; PRINTED CIRCUIT BOARDS; SPECTRUM ANALYZERS; SPURIOUS SIGNAL NOISE;

DECOUPLING CAPACITOR; SIGNAL INTEGRITY; VECTOR NETWORK ANALYZER;

ELECTROMAGNETIC COMPATIBILITY;

EID: 0033320005     PISSN: 10774076     EISSN: 21581118     Source Type: Conference Proceeding    
DOI: 10.1109/ISEMC.1999.812927     Document Type: Conference Paper

References (5)

1. C. O'Sullivan, L. Smith, D. Forehand, "Developing a Decoupling Methodology with SHOE for Multilayer Printed Circuit Boards", Proceedings of the IEEE International Symposium on EMC, Denver, Colorado, August 24-28, 1998.
2. B. Archambeault, P. Wetmore, X. Yuan, R. Mathews, "Modeling the Effectiveness of Decoupling Capacitors for Multilayer PCBs". Proceedings of the IEEE International Symposium on EMC, Austin, Texas, August 18-22, 1997.
3. L. Smith, "Decoupling Capacitor Calculations for CMOS Circuits," Electrical Performance of Electronic Packaging Conference, Nov. 1994.
4. HSPICE, Meta-Software, Inc., Campbell, CA.
5. T. Roy, L. Smith and J. Prymak, "ESR and ESL of Ceramic Capacitor Applied to Decoupling Applications," Electrical Performance of Electronic Packaging Conference, Oct. 1998.