Cache memories for dataflow systems

IEEE Parallel and Distributed Technology

Volumn 4, Issue 4, 1996, Pages 50-64

  Hurson, A R ^a   Kavi, Krishna M ^a   Shirazi, Behrooz ^a   Lee, Ben ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER SYSTEMS PROGRAMMING; PARALLEL PROCESSING SYSTEMS; PROCESS CONTROL; PROGRAM COMPILERS; PROGRAM PROCESSORS; SEQUENTIAL SWITCHING; STORAGE ALLOCATION (COMPUTER); VIRTUAL STORAGE;

CACHE MISSES; CONTEXT SWITCHING; DATAFLOW SYSTEMS; MEMORY LATENCIES; MULTITHREADING; THROUGHPUT;

BUFFER STORAGE;

EID: 0030418942     PISSN: 10636552     EISSN: None     Source Type: Journal    
DOI: 10.1109/88.544436     Document Type: Article

References (13)

1. G.R. Gao L. Bic J.L. Gaudiot Advanced Topics in Dataflow Computing and Multithreading, 1995 Los Alamitos, Calif.,