Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 19, Issue 3, 1998, Pages 243-256

  Chang, Yun Nan ^a,c,d   Wang, Ching Y I ^b,d,e,f,g   Parhi, Keshab K ^a,d,h,i,j  

^a University of Minnesota   (United States)

^b Theseus Logic Inc   (United States)

^c NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^d UNIVERSITY OF MINNESOTA   (United States)

^e SANDIA NATIONAL LABORATORIES   (United States)

^f UNIVERSITY OF IDAHO   (United States)

^g IEEE   (United States)

^h INDIAN INSTITUTE OF TECHNOLOGY   (India)

ⁱ UNIVERSITY OF PENNSYLVANIA   (United States)

^j UNIVERSITY OF CALIFORNIA   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CLOSED LOOP CONTROL SYSTEMS; FUNCTIONS; HEURISTIC METHODS; LINEAR PROGRAMMING; MATHEMATICAL MODELS; RESOURCE ALLOCATION; SCHEDULING; INTEGER PROGRAMMING; ITERATIVE METHODS;

ALLOCATION ALGORITHMS; HETEROGENEUOS FUNCTIONAL UNITS; HIGH-LEVEL SYNTHESIS; OPTIMAL SOLUTIONS; HEURISTIC FUNCTIONAL UNITS;

DIGITAL SIGNAL PROCESSING;

EID: 0032141050     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (37)

1. M.C. McFarland, A.C. Parker, and R. Camposano, "The highlevel synthesis of digital systems," Proceedings of the IEEE, Vol. 78, pp. 301-318, Feb. 1990.
2. C.-Y. Wang and K.K. Parhi, "High-level DSP synthesis," in Microsystems Technology for Multimedia Applications, B. Sheu, M. Ismail, E. Sanchez-Sinencio, and T.H. Wu (Eds.), IEEE Press, Chapt. 8.2, pp. 615-627, 1995.
3. R. Camposano and W. Wolf (Eds.), High Level VLSI Synthesis, Kluwer Academic Publishers, 1991.
4. M. A. Bayoumi (Ed.), VLSI Design Methodologies for Digital Signal Processing Architectures, Kluwer Academic Publishers, 1991.
5. J. Vanhoof, I. Bolsens, G. Goosens, H.J. De Man, and K. Rompaey, High Level Synthesis for Real-Time Digital Signal Processing, Kluwer Academic Press, 1993.
6. H. De Man et al., "Architecture driven synthesis techniques for VLSI implementation of DSP algorithms," Proceedings of the IEEE, pp. 319-335, Feb. 1990.
7. L.-F. Chao, A. LaPaugh, and E. Sha, "Rotation scheduling," in Design Automation Conference, pp. 566-572, June 1993.
8. T.A. Ly and J.T. Mowchenko, "Applying simulated evolution to high-level synthesis," IEEE Transactions on Computer-Aided Design, pp. 389-409, March 1993.
9. C.-T. Hwang and Y.-C. Hsu, "Zone scheduling," IEEE Transactions on Computer-Aided Design, Vol. 12, pp. 926-934, July 1993.
10. J. Biesenack et al., "The siemens high-level synthesis system callas," IEEE Transactions on VLSI Systems, Vol. 1, Sept. 1993.
11. I.-C. Park and C.-M. Kyung, "FAMOS: An efficient scheduling algorithm for high-level synthesis," IEEE Transactions on Computer-Aided Design, Vol. 12, pp. 1437-1448, Oct. 1993.
12. T.-F. Lee, A.C.-H. Wu, D.D. Gajski, and Y.-L. Lin, "A transformation-based method for loop folding," IEEE Transactions on Computer-Aided Design, Vol. 13, pp. 439-450, April 1994.
13. S. Amellal and B. Kaminska, "Functional synthesis of digital systems with TASS," IEEE Transactions on Computer-Aided Design, Vol. 13, pp. 537-552, May 1994.
14. C.-Y. Wang and K.K. Parhi, "High-level synthesis using concurrent transformations, scheduling, and allocation," IEEE Transactions on Computer-Aided Design, Vol. 14, pp. 274-295, March 1995.
15. C.-Y. Wang and K.K. Parhi, "Resource-constrained loop list scheduler for DSP algorithms," Journal of VLSI Signal Processing, Vol. 11, pp. 75-96, Oct./Nov. 1995.
16. B.S. Haroun and M.I. Elmasry, "Architecural synthesis for DSP silicon compilers," IEEE Transactions on Computer-Aided Design, Vol. 8, pp. 431-447, April 1989.
17. J. Rabaey, C.-M. Chu, P. Hoang, and M. Potkonjak, "Fast prototyping of datapath-intensive architectures," IEEE Design and Test, Vol. 8, pp. 40-51, June 1991.
18. L. Ramachandran and D.D. Gajski, "An algorithm for component selection in performanced optimized scheduling," in International Conference on Computer-Aided Design, Santa Clara, CA, pp. 92-95, Nov. 1991.
19. A.H. Timmer and J.A. Jess, "Execution interval analysis under resource constraints," in International Conference on ComputerAided Design, pp. 454-459, Nov. 1993.
20. M. Ishikawa and G. De Micheli, "A module selection algorithm for high-level synthesis," in International Symposium on Circuits and Systems, Singapore, pp. 1777-1780, June 1991.
21. C.-T. Hwang, J.-H. Lee, and Y.-C. Hsu, "A formal approach to the scheduling problem in high-level synthesis," IEEE Transactions on Computer-Aided Design, Vol. 10, pp. 464-475, April 1991.
22. C. Hwang et al., "PLS: Scheduler for pipeline synthesis," IEEE Transactions on Computer-Aided Design, Vol. 12, pp. 1279-1286, Sept. 1993.
23. C.H. Gebotys and M. Elmasry, "Global optimization approach for architecture synthesis," IEEE Transactions on ComputerAided Design, Vol. 12, pp. 1266-1278, Sept. 1993.
24. C.H. Gebotys, "An optimization approach to the synthesis of multichip architectures," IEEE Transactions on VLSI Systems, Vol. 2, pp. 11-20, March 1994.
25. K. Ito, L.E. Lucke, and K.K. Parhi, "Module selection and data format conversion for cost-optimal DSP synthesis," in International Conference on Computer-Aided Design, San Jose, CA, pp. 322-329, Nov. 1994.
26. K. Ito and K.K. Parhi, "A generalized technique for register counting and its application to cost-optimal DSP architecture synthesis," Journal of VLSI Signal Processing, Vol. 16, pp. 57-72, May 1997.
27. E.A. Lee and D.G. Messerschmitt, "Static scheduling of synchronous data flow programs for digital signal processing," IEEE Transactions on Computers, Vol. 36, pp. 24-35, Jan. 1987.
28. M. Garey and D. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, Freeman and Co., 1979.
29. R.I. Hartley and J.R. Jasica, "Behavioral to structural translation in a bit-serial silicon compiler," IEEE Transactions on Computer-Aided Design, Vol. 7, pp. 877-886, Aug. 1988.
30. G.W. Leive and D.E. Thomas, "A technology relative logic synthesis and module selection system," in Design Automation Conference, pp. 479-485, 1981.
31. A.H. Timmer, M.J.M. Heijligers, L. Stok, and J.A. Jess, "Module selection and scheduling using unrestricted libraries," in European Design Automation Conference, pp. 547-551, 1993.
32. Y.-N. Chang, C.-Y. Wang, and K.K. Parhi, "DSP synthesis with heterogeneous functional units using the MARS-II system," in 29th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, pp. 109-116, Oct. 1995.
33. Y.-N. Chang, C.-Y. Wang, and K.K. Parhi, "Loop-list scheduling with heterogeneous functional units," in Great Lakes Symposium on VLSI, Ames, IA, pp. 2-7, March 1996.
34. K.K. Parhi and D.G. Messerschmitt, "Static rate-optimal scheduling of iterative data-flow programs via optimum unfolding," IEEE Trans. on Computers, Vol. 40, pp. 178-195, Feb. 1991.
35. M. Renfors and Y. Neuvo, "The maximum sampling rate of digital filters under hardware speed constraints," IEEE Transactions on Circuits and Systems, pp. 196-202, 1981.
36. E. Reingold et al., Combinatorial Algorithms - Theory and Practice, Prentice Hall, 1977.
37. C.-Y. Wang and K.K. Parhi, "MARS: A high-level DSP synthesis tool integrated within the mentor graphics environment," in Mentor Graphics Users Group, Portland, OR, Oct. 1995.