A high speed 3.3V IO buffer with 1.9V tolerant CMOS process

European Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 128-131

  Singh, Gajendra ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER DESIGN; CMOS PROCESSS; DESIGN TECHNIQUE; GATE OXIDE THICKNESS; GATE-OXIDE STRESS; HIGH SPEED; POWER SUPPLY; SIGNAL INTEGRITY;

CMOS INTEGRATED CIRCUITS; DESIGN; GATES (TRANSISTOR);

LOW POWER ELECTRONICS;

EID: 0005118009     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.1998.186225     Document Type: Conference Paper

References (4)

1. Neil H.E. Weste and Kamran Eshraghian, "Principles of CMOS VLSI design," 2nd ed., Addison-Wesley Publishing Company, California, pp. 41-96,156-167,262-370,1993.
2. Randall L. Geiger, Phillip E. Allen and Noel R. S trader, "VLSI design techniques for analog and digital circuits," McGraw-Hill Publishing Company, New York, 1990.
3. Roubik Gregorian and Gabor C. Temes, "Analog MOS integrated circuits for signal processing," John Wiley &Sons, New York, pp. 64-117,121-146,1986.
4. Edward S. Yang, "Microelectronic devices", McGraw-Hill, Inc., 1988.