High-speed silicon single-electron random access memory

IEEE Electron Device Letters

Volumn 20, Issue 11, 1999, Pages 583-585

  Stone, N J ^a   Ahmed, H ^a   Nakazato, K ^b  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

^b HITACHI CAMBRIDGE LABORATORY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; SEMICONDUCTING SILICON;

SINGLE ELECTRON TUNNELLING TRANSISTORS;

RANDOM ACCESS STORAGE;

EID: 0033221554     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.798051     Document Type: Article

References (7)

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3. S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, and E. F. Crabbé, "A silicon nanocrystals based memory," Appl. Phys. Lett., vol. 68, p. 1377, 1996.
4. K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F. Murai, and K. Seki, "A room temperature single-electron memory device using fine-grain polycrystalline silicon," in IEDM Tech. Dig., 1993, p. 541.
5. N. J. Stone and H. Ahmed, "Silicon single electron memory cell," Appl. Phys. Lett., vol. 73, p. 2134, 1998.
6. K. Nakazato and H. Ahmed, "The multiple-tunnel junction and its application to single-electron memory and logic-circuits," Jpn. J. Appl. Phys., vol. 34, pt. 1, no. 2B, p. 700, 1995.
7. R. A. Smith and H. Ahmed, "Gate controlled Coulomb blockade effects in the conduction of a silicon quantum wire," J. Appl. Phys., vol. 81, p. 2699, 1997.