Integrating performance monitoring and communication in parallel computers

Performance Evaluation Review

Volumn 24, Issue 1, 1996, Pages 138-147

  Martonosi, Margaret ^a   Ofelt, David ^b   Heinrich, Mark ^b  

^a Princeton University

^b Stanford University

Author keywords

[No Author keywords available]

Indexed keywords

CACHE COHERENCE; FLASHPOINT MONITORING TOOL; MEMORY HIERARCHY; MEMORY PERFORMANCE MONITORING;

BUFFER STORAGE; COMPUTER CONTROL SYSTEMS; COMPUTER HARDWARE; COMPUTER SOFTWARE; DATA ACQUISITION; DATA COMMUNICATION SYSTEMS; DATA STORAGE EQUIPMENT; DATA STRUCTURES; NETWORK PROTOCOLS; PERFORMANCE;

PARALLEL PROCESSING SYSTEMS;

EID: 0030146187     PISSN: 01635999     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/233008.233035     Document Type: Article

References (30)

1. +S] A. Agarwal, R. Bianchini, D. Chaiken, et al. The MIT Alewife Machine: Architecture and Performance. Proc. 22nd Int'l. Symp. on Computer Architecture. Jun, 1995.
2. +95] N. J. Boden, D. Cohen, R. E. Felderman, et al. Myrinet: A Gigabit-per-Second Local Area Network. IEEE Micro 15(1). pages 29-36. Feb., 1995.
3. +94] M. A. Blumrich, K. Li, R. Alpert, et al. Virtual Memory Mapped Network Interface for the SHRIMP Multicomputer. Proc. 21st Int'l. Symp. on Computer Architecture. pages 141-153. April, 1994.
4. [BM89] H. Burkhart and R. Millen. Performance-Measurement Tools in a Multiprocessor Environment. IEEE Trans. on Computers, 38(5):725-737, May 1989.
5. +94] R. Chandra, S. Devine, B. Verghese, et al. Scheduling and Page Migration for Multiprocessor Compute Servers. In Proc. 6th Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, pages 12-24, Oct. 1994.
6. +92] D. Dobberpuhl et al. A 100MHz 64b Dual-issue CMOS Microprocessor. In Int'l Solid State Circuits Conf. Digest of Technical Papers, Feb 1992.
7. [DBK+90] J. Dongarra, O. Brewer, J. A. Kohl and S. Fineberg.A Tool to Aid in the Design, Implementation, and Understanding of Matrix Algorithms for Parallel Processors. Journal of Parallel and Distributed Computing. pages 185-202. Jun, 1990.
8. [DEC92] DEC. DECChip 21064 RISC Microprocessor Preliminary Data Sheet. Technical report, 1992.
9. [GH93] A.J. Goldberg and J. L. Hennessy. Mtool: An Integrated System for Performance Debugging Shared Memory Multiprocessor Applications. IEEE Trans. on Parallel and Distributed Systems, pages 28-80, Jan.1993.
10. [Gol93] S. R. Goldschmidt. Simulation of Multiprocessors, Speed and Accuracy. Ph.D. Thesis, Stanford University, June, 1993.
11. [JHei95] J. Heinrich. MIPS R1000 Microprocessor User's Manual. 1995.
12. [Hei93] M. Heinrich. DASH Performance Monitor Hardware Documentation. Stanford University, Unpublished Memo. 1993.
13. [HGD+94] J. Heinlein, K. Gharachorloo, S. Dresser, et al. Integration of Message Passing and Shared Memory in the Stanford FLASH Multiprocessor. In Proc. 6th Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, pages 38-50, Oct. 1994.
14. +94] M. Heinrich, J. Kuskin, D. Ofelt, et al. The Performance Impact of Flexibility in the Stanford FLASH Multiprocessor. In Proc. 6th Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, pages 274-285, Oct. 1994.
15. [HLW95] M. D. Hill, J. R. Larus, and D. A. Wood. Tempest: A Substrate for Portable Parallel Programs. Proc. Compcon. March, 1995.
16. +96] M. Horowitz, M. Martonosi, T. Mowry, M. D. Smith. Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors. Proc. 23rd Int'l. Symp. on Computer Architecture., May, 1996.
17. [HP90] J. Hennessy and D. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 1990.
18. +94] J. Kuskin, D. Ofelt, M. Heinrich, et al. The Stanford FLASH Multiprocessor. Proc. 21st Int'l. Symp. on Computer Architecture, Apr.1994.
19. [LW94] A. R. Lebeck and D. A. Wood. Cache Profiling and the SPEC Benchmarks: A Case Study. IEEE Computer, October 1994.
20. [Mar93] M. Martonosi. Analyzing and Tuning Memory Performance in Sequential and Parallel Programs. Ph.D. Thesis, Stanford Univ., Dec. 1993.
21. [MGA95] M. Martonosi, A. Gupta and T. Anderson. Effectiveness of Trace Sampling for Performance Debugging Tools. Proc. ACM SIGMETRICS Conf. on Measurement and Modeling of Computer Systems. May, 1993.
22. [Mat94] Terje Mathison. Pentium Secrets. Byte, pages 191-192, July 1994.
23. +94] A. Nowatzyk, G. Aybay, M. Browne, et al. The S3.mp Scalable Shared Memory Multiprocessor. Proc. 27th Hawaii Int'l Conf. on System Sciences Vol. I: Architecture, pages 144-53. Jan, 1994.
24. [RLW94] S. K. Reinhardt, J. R. Larus and D. A. Wood. Tempest and Typhoon: User-Level Shared Memory. Proc. 21st Int'l. Symposium on Computer Architecture. April, 1994.
25. [Sim92] R. Simoni. Cache Coherence Directories for Scalable Multiprocessors. Ph.D. Thesis, Stanford Univ., Nov. 1992.
26. [Smi92] M. D. Smith. Support for Speculative Execution in High-Performance Processors. Ph.D. Thesis, Stanford Univ., Nov. 1992.
27. [SJH89] M. D. Smith, M. Johnson, and M. Horowitz. Limits on Multiple Instruction Issue. Proc. 3rd Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, 1989, pages 290-302.
28. [Stall93] R. Stallman. Using and Porting GNU CC. Free Software Foundation, Cambridge, MA, June 1993.
29. +95] S. Woo, M. Ohara, E. Torrie, et al. Methodological Considerations and Characterization of the SPLASH-2 Parallel Application Suite. Proc. 22nd Int'l. Symp. on Computer Architecture. Jun, 1995.
30. [ZH88] B. Zorn and P. N. Hilfinger. A Memory Allocation Profiler for C and Lisp. Technical Report UCB/CSD 88/404, Feb. 1988.