Low-power divider

IEEE Transactions on Computers

Volumn 48, Issue 1, 1999, Pages 2-14

  Nannarelli, Alberto ^a,b   Lang, Tomás ^a,b  

^a IEEE   (United States)

^b University of California at Irvine   (United States)

Author keywords

Digit recurrence division; Floating point division; Low power

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; ENERGY DISSIPATION; ENERGY UTILIZATION;

DIGIT-RECURRENCE DIVISIONS; FLOATING-POINT DIVISIONS; LOW-POWER DIVIDERS;

DIVIDING CIRCUITS (ARITHMETIC);

EID: 0032737807     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.743407     Document Type: Article

References (12)

1. A. Prabhu and G. Zyner, "167 MHz Radix-8 Divide and Square Root Using Overlapped Radix-2 Stages," Proc. 12th Symp. Computer Arithmetic, pp. 155-162, July 1995.
2. N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, second ed. Addison-Wesley, 1993.
3. A.P. Chandrakasan and R.W. Brodersen, Low Power Digital CMOS Design. Kluwer Academic, 1995.
4. J.M. Rabaey et al., Low Power Design Methodologies. Kluwer Academic, 1996.
5. M.D. Ercegovac and T. Lang, Division and Square Root: Digit-Recurrence Algorithms and Implementations. Kluwer Academic, 1994.
6. Compass Design Automation, Passport - 0.6-Micron, 3-Volt, High-Performance Standard Cell Library. Compass Design Automation, Inc., 1994.
7. A. Nannarelli, "PET: Power Evaluation Tool," http://www.eng.uci.edu/ numlab/PET/, Aug. 1996.
8. A. Nannarelli and T. Lang, "Low-Power Radix-8 Divider," Proc. Int'l Conf. Computer Design, pp. 420-426, Oct. 1998.
9. I. Koren, Computer Arithmetic Algorithms. Prentice Hall, 1993.
10. J. Monteiro, S. Devadas, and A. Ghosh, "Retiming Sequential Circuits for Low Power," Proc. 1993 Int'l Conf. Computer-Aided Design (ICCAD), pp. 398-402, Nov. 1993.
11. K. Usami and M. Horowitz, "Clustered Voltage Scaling Technique for Low-Power Design," Proc. Int'l Symp. Low Power Design, pp. 3-8, Apr. 1995.
12. T. Lang, E. Musoll, and J. Cortadella, "Individual Flip-Flops with Gated Clocksfor Low-Power Datapaths," IEEE Trans. Circuits and Systems, pp. 507-516, June 1997.