Fast fault translation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 1, 1998, Pages 122-133

  Vinnakota, Bapiraju ^a,b   Andrews, Jason ^b  

^a IEEE   (United States)

^b UNIVERSITY OF MINNESOTA   (United States)

Author keywords

ATPG; Fault simulation; Fault translation; Functional test generation; Test generation

Indexed keywords

ALGORITHMS; GATES (TRANSISTOR); SEQUENTIAL CIRCUITS;

AUTOMATIC TEST PATTERN GENERATION (ATPG);

INTEGRATED CIRCUIT TESTING;

EID: 0032028339     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.661254     Document Type: Article

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