Improving the efficiency of BDD-based operators by means of partitioning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 5, 1999, Pages 545-556

  Cabodi, Gianpiero ^a   Camurati, Paolo ^a   Quer, Stefano ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; FINITE AUTOMATA; MATHEMATICAL OPERATORS; OPTIMIZATION;

BINARY DECISION DIAGRAMS (BDD); DYNAMIC PARTITIONING STRATEGY; FINITE STATE MACHINE (FSM);

DECISION THEORY;

EID: 0032672712     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.759068     Document Type: Article

References (16)

1. G. Cabodi, P. Camurati, and S. Quer, "Decomposed symbolic forward traversais of large finite state machine," in Proc. IEEE EURO-DAC'96, Geneva, Switzerland, Sept. 1996, pp. 170-175.
2. "Improved reachability analysis of large finite state machine," in Proc. IEEE/ACMICCAD'96, San Jose, CA, Nov. 1996, pp. 354-360.
3. "Memory optimization in function and set manipulation with BDD's," Software-Practice and Experience, vol. 28, no. 11, pp. 99-120, June 1998.
4. R.E. Bryant, "Graph-based algorithms for Boolean function manipulation," IEEE Trans. Computers, vol. C-35, pp. 677-691, Aug. 1986.
5. "Symbolic Boolean manipulation with ordered binary-decision diagrams," ACM Computing Surveys, vol. 24, no. 3, pp. 293-318, Sept. 1992.
6. J. Jain, J. Bitner, J.A. Abraham, and D.S. Fussel, "Functional partitioning for verification and related problems," in Proc. Brown/MIT VLSI Conference, Mar. 1992, pp. 210-226.
7. A. Narayan, J. Jain, M. Fujita, and A. Sangiovanni-Vincentelli, "Partitioned ROBDD's-A compact, canonical and efficient manipulable representation of Boolean functions," in Proc. IEEE/ACM ICCAD'96, San Jose, CA, Nov. 1996, pp. 547-554.
8. J.R. Burch, E.M. Clarke, D.E. Long, K.L. McMillan, and D.L. Dill, "Symbolic model checking for sequential circuit verification," IEEE Trans. Computer-Aided Design, vol. 13, no. 4, pp. 401-124, Apr. 1994.
9. K. Ravi and F. Somenzi, "High-density reachability analysis," in Proc. IEEE/ACMICCAD'95, San Jose, CA, Nov. 1995, pp. 154-158.
10. R.E. Bryant, "Binary decision diagrams and beyond: Enabling tech-nologies for formal verification," in Proc. IEEE/ACM ICCAD'95, San Jose, CA, Nov. 1995, pp. 236-243.
11. A. Narayan, A.J. Isles, J. Jain, R.K. Brayton, and A. SangiovanniVincentelli, "Reachability analysis using partitioned-ROBDD's," in Proc. IEEE/ACMICCAD'97. San Jose, CA, Nov. 1997, pp. 388-393.
12. F. Somenzi, "CUDD: CU decision diagram package-Release 2.2.0," Dept. Elect, and Comput. Eng., Univ. Colorado, Boulder, CO, Tech. Rep., May 1998.
13. J. Bern, C. Meinel, and A. Slobodova", "Some heuristics for generating tree-like FBDD types," IEEE Trans. Computer-Aided Design, vol. 15, pp. 127-131, Jan. 1996.
14. K.J. Englert, "Heuristische Verfahren zur Generierung von FBDDTypen," M.S. thesis, Univ. Freiburg, Freiburg, Germany, 1995.
15. M. Tachibana, "Heuristic algorithms for FBDD node minimization with application to pass-transistor-logic and DCVS synthesis," in Proc. SASIMI'96, Fuknoka, Kyushu, Japan, Nov. 1996.
16. G. Cabodi, P. Camurati, L. Lavagno, and S. Quer, "Verification and synthesis of counters based on symbolic techniques," in Proc. EDAA/ACM/IEEE ED&TC'97, Paris, France, Mar. 1997, pp. 176-181.