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Volumn 14, Issue 6, 1999, Pages 489-495

New analytical model to determine the drain-source series resistance of FOLD MOSFET

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CONDUCTANCE; ELECTRIC FIELD EFFECTS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); HOT CARRIERS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; TRANSCONDUCTANCE; TRANSIT TIME DEVICES;

EID: 0032672648     PISSN: 02681242     EISSN: None     Source Type: Journal    
DOI: 10.1088/0268-1242/14/6/301     Document Type: Article
Times cited : (10)

References (15)
  • 4
    • 0019049847 scopus 로고
    • Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor
    • Ogura S, Tsang P J, Walker W W, Critchlow D L and Shepard J F 1980 Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor IEEE Trans. Electron Devices 27 1359-67
    • (1980) IEEE Trans. Electron Devices , vol.27 , pp. 1359-1367
    • Ogura, S.1    Tsang, P.J.2    Walker, W.W.3    Critchlow, D.L.4    Shepard, J.F.5
  • 5
    • 0022217294 scopus 로고
    • An analytical one-dimensional model for lightly doped drain (LDD) MOSFET devices
    • Lai F-S J and Sun J Y-C 1985 An analytical one-dimensional model for lightly doped drain (LDD) MOSFET devices IEEE Trans. Electron Devices 32 2803-11
    • (1985) IEEE Trans. Electron Devices , vol.32 , pp. 2803-2811
    • Lai, F.S.J.1    Sun, J.Y.C.2
  • 7
    • 0023548487 scopus 로고
    • The impact of gate-drain overlapped LDD (GOLD) for deep submicron VLSIs
    • Izawa R, Kure T, Iijima S and Takeda E 1987 The impact of gate-drain overlapped LDD (GOLD) for deep submicron VLSIs IEEE IEDM Technol. Dig. 38-41
    • (1987) IEEE IEDM Technol. Dig. , pp. 38-41
    • Izawa, R.1    Kure, T.2    Iijima, S.3    Takeda, E.4
  • 8
    • 0001177570 scopus 로고
    • A new MOSFET with large-tilt-angle implanted drain (LATID) structure
    • Hori T and Kurimoto K 1988 A new MOSFET with large-tilt-angle implanted drain (LATID) structure IEEE Electron Device Lett. 9 300-2
    • (1988) IEEE Electron Device Lett. , vol.9 , pp. 300-302
    • Hori, T.1    Kurimoto, K.2
  • 12
    • 0023366571 scopus 로고
    • An analytic I-V model for lightly doped drain (LDD) MOSFET devices
    • Huang G-S and Wu C-Y 1987 An analytic I-V model for lightly doped drain (LDD) MOSFET devices IEEE Trans. Electron Devices 34 1311-21
    • (1987) IEEE Trans. Electron Devices , vol.34 , pp. 1311-1321
    • Huang, G.-S.1    Wu, C.-Y.2
  • 14
    • 0020269013 scopus 로고
    • Simple model for the overlap capacitance of a VLSI MOS device
    • Shrivastava R and Fitzpatric K 1982 Simple model for the overlap capacitance of a VLSI MOS device IEEE Trans. Electron Devices 29 1870-5
    • (1982) IEEE Trans. Electron Devices , vol.29 , pp. 1870-1875
    • Shrivastava, R.1    Fitzpatric, K.2
  • 15
    • 0022238238 scopus 로고
    • An accurate mobility model for the I-V characteristics of n-channel enhancement-mode MOSFETs with single-channel boron implantation
    • Wu C Y and Daih Y W 1985 An accurate mobility model for the I-V characteristics of n-channel enhancement-mode MOSFETs with single-channel boron implantation Solid State Electron. 28 1271-8
    • (1985) Solid State Electron. , vol.28 , pp. 1271-1278
    • Wu, C.Y.1    Daih, Y.W.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.