Concurrency preserving partitioning algorithm for parallel logic simulation

VLSI Design

Volumn 9, Issue 3, 1999, Pages 253-270

  Kim, Hong K ^a,b,c,d,e   Jean, Jack ^a,f,g,h  

^a Wright State University   (United States)

^b WRIGHT STATE UNIVERSITY   (United States)

^c NEW JERSEY INSTITUTE OF TECHNOLOGY   (United States)

^d Korea University   (South Korea)

^e ACM   (United States)

^f NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^g UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^h NATIONAL SCIENCE FOUNDATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; COMPUTER SOFTWARE; LOGIC DESIGN; LOGIC GATES;

CONCURRENCY PRESERVING PARTITIONING ALGORITHM; DISCRETE EVENT SIMULATION; PARALLEL LOGIC SIMULATION; TIME WARP;

PARALLEL ALGORITHMS;

EID: 0032665642     PISSN: 1065514X     EISSN: None     Source Type: None    
DOI: 10.1155/1999/18373     Document Type: Article

References (26)

1. Bailey, M. L., Briner, J. V. Jr. and Chamberlain, R. D. (1994). "Parallel Logic Simulation of VLSI Systems", ACM Computing Surveys, 26(3), 255-294.
2. Brglez, F., Bryan, D. and Kozminski, K. (1989). "Combinational Profiles of Sequential Benchmark Circuits", Proc. of the IEEE International Symp. on Circuits and Systems, pp. 1929-1934.
3. Boukerche, A. and Tropper, C. (1994). "A Static Partitioning and Mapping Algorithm for Conservative Parallel Simulations", Proc. of 8th Workshop on Parallel and Distributed Simulation, pp. 164-172.
4. Boukerche, A. and Tropper, C. (1995). "SGTNE: Semi-Global Time of the Next Event Algorithm," Proc. of 9th Workshop on Parallel and Distributed Simulation, pp. 68-77.
5. Briner, J. V. Jr. (1990). "Parallel Mixed-Level Simulation of Digital Circuits Using Virtual Time," Ph.D. Dissertation, Duke University.
6. Chamberlain Roger, D. and Henderson Cheryl, D. (1994). "Evaluating the Use of Pre-Simtilation in VLSI Circuit Partitioning," Proc. of 8th Workshop on Parallel and Distributed Simulation, pp. 139-146.
7. Fiduccia, C. M. and Mattheyses, R. M. (1982). "A Linear-Time Heuristic for Improving Network Partitions," Proc. of the Design Automation Conference, pp. 175-181.
8. Jefferson, D. R. (1985). "Virtual Time," ACM Trans. on Programming Languages and Systems, 7(3), 404-425.
9. Vikas Jha and Rajive Bagrodia (1996). "A Performance Evaluation Methodology for Parallel Simulation Protocols," Proc. of 10th Workshop on Parallel and Distributed Simulation, pp. 180-185.
10. Kapp, K. L., Hartrum, T. C. and Wailes, T. S. (1995). "An Improved Cost Function for Static Partitioning of Parallel Circuit Simulations Using a Conservative Synchronization Protocol," Proc. of 9th Workshop on Parallel and Distributed Simulation, pp. 78-85.
11. Karypis, G. and Kumar, V. (1995). "Multilevel graph partition and sparse matrix ordering," Int'l Conf on Parallel Processing, 3, 113-122.
12. Keller, J., Rauber, T. and Rederlechner, B. (1996). "Conservative Circuit Simulation on Shared-Memory Multiprocessors," Proc. of 10th Workshop on Parallel and Distributed Simulation, pp. 126-134.
13. Kernighan, B. W. and Lin, S. (1970). "An Efficient Heuristic Procedure for Partitioning Graphs," Bell System Technical Journal, 49, pp. 291-307.
14. Hong, K., Kim and Jack, Jean (1996). "Concurrency Preserving Partitioning (CPP) for Parallel Logic Simulation," Proc. of 10th Workshop on Parallel and Distributed Simulation, pp. 98-105.
15. Pavlos, Konas and Pen-Chung, Yew (1991). "Parallel Discrete Event Simulation on Shared-Memory Multiprocessors," The 24th Annual Simulation Symposium, pp. 134-148.
16. Kravitz, S. A. and Ackland, B. D. (1988). "Static vs. Dynamic Partitioning of Circuits for a MOS Timing Simulator on A Message-Based Multiprocessor," Proc. of the SCS Multiconference on Distributed Simulation, pp. 136-140.
17. Levendel, V. H., Menon, P. R. and Patel, S. H. (1982). "Special Purpose Computer for Logic Simulation Using Distributed Processing," Bell System Technical Journal, 61(10), 2873-2909.
18. Yi-Bing, Lin (1992). "Parallelism analyzers for parallel discrete event simulation," ACM Transactions on Modeling and Computer Simulation, pp. 239-264.
19. Malloy, B. A., Lloyd, E. L. and Soffa, M. L. (1994). "Scheduling DAG's for Asynchronous Multiprocessor Execution," IEEE Transactions on Parallel and Distributed Systems, 5(5), 495-508.
20. Manjikian, N. and Loucks, W. M. (1993). "High Performance Parallel Logic Simulation on a Network of Workstations," Proc. of 7th Workshop on Parallel and Distributed Simulation, pp. 76-84.
21. Mueller-Thuns, R. B., Saab, D. G., Damiano, R. F. and Abraham, J. A. (1993). "VLSI Logic and Fault Simulation on General-Purpose Parallel Computers," IEEE Trans. on Computer-Aided Design, 12(3), 446-460.
22. Biswajit Nandy and Loucks, W. M. (1992). "An Algorithm for Partitioning and Mapping Conservative Parallel Simulation onto Multicomputers," Proc. of 6th Workshop on Parallel and Distributed Simulation, pp. 139-146.
23. Laura, A., Sanchis (1989). "Multiple-Way Network Partitioning," IEEE Transactions on Computers, 38(1), 62-81.
24. Smith, S. P., Underwood, B. and Mercer, M. R. (1987). "An Analysis of Several Approaches to Circuit Partitioning for Parallel Logic Simulation," IEEE International Conference on Computer Design, pp. 664-667.
25. Soule, L. and Gupta, A. (1989). "Characterization of Parallelism and Deadlocks in Distributed Digital Logic Simulation," Proc. of the 26th Design Automation Conf., pp. 81-86.
26. Sporrer, C. and Bauer, H. (1993). "Corolla Partitioning for Distributed Logic Simulation of VLSI-Circuits," Proc. of 7th Workshop on Parallel and Distributed Simulation, pp. 85-92.