Concurrency preserving partitioning (CPP) for parallel logic simulation

Parallel and Distributed Simulation, Workshop Proceedings

Volumn , Issue , 1996, Pages 98-105

  Kim, Hong K ^a   Jean, Jack ^a  

^a WRIGHT STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTATIONAL METHODS; CONCURRENCY CONTROL; LOGIC CIRCUITS; LOGIC GATES; PARALLEL PROCESSING SYSTEMS; PERFORMANCE;

CIRCUIT SIMULATION; CONCURRENCY PRESERVING PARTITIONING; DIRECTED GRAPH; INTERPROCESSOR COMMUNICATION; LOAD BALANCING; PARALLEL GATE LEVEL CIRCUIT SIMULATOR; PARALLEL LOGIC SIMULATION; TIME WARP;

COMPUTER SIMULATION;

EID: 0029711793     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/238793.238823     Document Type: Conference Paper

References (17)