Analysis of external latch-up protection test structure design using numerical simulation

Microelectronics Reliability

Volumn 39, Issue 5, 1999, Pages 647-659

  Palser, Kevin ^a   Concannon, Ann ^a   Duffy, Ray ^a   Mathewson, Alan ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC DISCHARGES; ELECTROSTATICS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING;

EXTERNAL LATCH-UP PROTECTION TEST PATTERN DESIGN;

FLIP FLOP CIRCUITS;

EID: 0032661013     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(99)00046-3     Document Type: Article

References (5)

1. Troutman R.R. Latchup in CMOS technology, the problem and its cure. 1986;Kluwer, Dordrecht.
2. Quinke J. Novel test structures for the investigation of the effiency of guard rings used for I/O-latch-up prevention. Proceedings of IEEE 1990 International Conference on Microelectronic Test Structures, vol. 3 :1990;35-39.
3. Quinke J. Analysis of latch-up neighborhood effects in VLSI CMOS input and output stages. Microelectronics and Reliability. 30:(1):1989;105-122.
4. Menozzi R., Selmi L., Sangirorgi E., Riccò B. Effects of the interaction of neighboring structures on the latch-up behavior of C-MOS IC's. IEEE Transactions on Electron Devices. 38:(8):1991;1978-1981.
5. Pavan P., Pellesi A., Meneghesso G., Zanoni E. Affects of ESD protection on latch-up sensitivity of CMOS 4-stripe structures. Microelectronics Reliability. 37:(10/11):1997;1561-1564.