Effects of esd protections on latch-up sensitivity of CMOS 4-stripe structures

Microelectronics Reliability

Volumn 37, Issue 10-11, 1997, Pages 1561-1564

  Pavan, P ^a   Pellesi, A ^a   Meneghesso, G ^b   Zanoni, E ^b  

^a UNIVERSITY OF MODENA AND REGGIO EMILIA   (Italy)

^b UNIVERSITY OF PADOVA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; MOS DEVICES; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DIODES; SUBSTRATES;

GUARD RING; LATCH UP SENSITIVITY;

CMOS INTEGRATED CIRCUITS;

EID: 0031249210     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(97)00109-1     Document Type: Article

References (2)

1. P. Pavan, E. Zanoni, R. Menozzi, L. Selmi, "Adjacent structure interactions in latch-up dc triggering of CMOS twin-tub and epitaxial technologies", Proc. ESREF 91, Bordeaux (France), pp. 333-338, Oct. 7-10, 1991.
2. F. Fantini, M. Muschitiello, E. Zanoni, "Latch-up in CMOS Integrated Circuits", in "Microelectronics Reliability", vol II E. Pollino Ed., Artech House, Norwood, MA, USA, 1989.