A low-power and high-speed dynamic PLA circuit configuration for single-clock CMOS

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 46, Issue 7, 1999, Pages 857-861

  Wang, Chua Chin ^a   Wu, Chi Feng ^a   Hwang, Rain Ted ^a   Kao, Chia Hsiung ^a  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

Author keywords

High speed; Low power; NOR NOR PLA; Single clock

Indexed keywords

BOOLEAN FUNCTIONS; COMBINATORIAL CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; LOGIC GATES; SEQUENTIAL CIRCUITS; TIMING CIRCUITS; VLSI CIRCUITS;

NAND GATES; POWER DISSIPATION; PROGRAMMABLE LOGIC ARRAYS;

CMOS INTEGRATED CIRCUITS;

EID: 0032659136     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.774233     Document Type: Article

References (5)

1. M. Afghahi, A robust single phase clocking for low power, high-speed VLSI applications, IEEE J. Solid-State Circuits, vol. 31, pp. 247-253, Feb. 1996.
2. G. M. Blair, PLA design for single-clock CMOS, IEEE J. Solid-State Circuits, vol. 27, pp. 1211-1213, Aug. 1992.
3. Y. B. Dhong and C. P. Tsang, High speed CMOS POS PLA using predischarged OR array and charge sharing AND array, IEEE Trans. Circuits Syst. //, vol. 39, pp. 557-564, Aug. 1992.
4. N. F. Goncalves and H. J. De Man, NORA: A race-free dynamic CMOS technology for pipelined logic structures, IEEE J. Solid-State Circuits, vol. 18, pp. 261-266, June 1983.
5. N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design-A Systems Perspective, 2nd ed. Reading, MA: Addison-Wesley, 1993.