Delay insensitive RSFQ circuits with zero static power dissipation

IEEE Transactions on Applied Superconductivity

Volumn 9, Issue 2 PART 3, 1999, Pages 3535-3538

  Polonsky, Stas ^a  

^a STONY BROOK UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC LOSSES; ELECTRIC POTENTIAL; ELECTRIC POWER DISTRIBUTION; ELECTRIC RESISTANCE; INTEGRATED CIRCUIT LAYOUT; JOSEPHSON JUNCTION DEVICES; SCHEMATIC DIAGRAMS;

DELAY INSENSITIVE; RAPID SINGLE FLUX QUANTUM CIRCUITS; RESISTOR FREE CURRENT DISTRIBUTION NETWORK;

LOGIC CIRCUITS;

EID: 0032654183     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/77.783793     Document Type: Article

References (8)

1. K. Likhaiev, "Recent progress and prospects of superconductor digital technology", FED report, January 1997.
2. A.V. Rylyakov, "Ultea-low-power RSFQ Devices and Digital Autocorrelation of Broadband Signals", Ph.D. thesis, Physics Department, SUNY-Stony Brook, May 1997.
3. P. Patra, S. Polonsky, D. Fussel, "Delay Insensitive Logic for Superconductor Technology, Extended Abstracts of ISEC'97, Eindhoven, The Netherlands, pp. 42-53, April 1997.
4. J.Z. Deng, S.R. Whiteley, and T. Van Duzer, "Data-driven self-timing of RSFQ digital integrated circuits", Extended Abstracts of ISEC'95, Nagoya, Japan, p. 189,1995.
5. A.V. Rylyakov, S.V. Polonsky "All-Digital 1-bit RSFQ Autocorrelator for Radioastronomy Applications: Design and Experimental Results:", IEEE Transactions onAppl. Supercond., vol. 8, no.l, p. 14-19,1998.
6. Y. Kameda, S. Polonsky, M. Maezawa, T. Nanya, "Self-timed parallel adders based on DI RSFQ primitives", report EOD-04 at this conference.
7. K.K. Likharev and V. K. Semenov, "RSFQ logic/memory family: A new Josephsonjunction technology for subterahertzclock frequency digital systems," IEEE Trans. Appl. Supercond., vol. 1, no. 1, pp. 3-28, Mar. 1991.
8. P. Patra, "Approaches to Design of Circuits for Low-Power Computation", Ph.D. thesis, The University of Texas at Austin, 1995.