Temperature-Dependent Bitor Rate of a Clocked Superconducting Digital Circuit

IEEE Transactions on Applied Superconductivity

Volumn 9, Issue 2 PART 3, 1999, Pages 3594-3597

  Herr, Quentin P ^a,b   Johnson, Mark W ^a   Feldman, Marc J ^a  

^a University of Rochester   (United States)

^b NORTHROP GRUMMAN CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; DIGITAL CIRCUITS; ELECTRIC CURRENTS; ERROR DETECTION; EXTRAPOLATION; FLIP FLOP CIRCUITS; TEMPERATURE; THERMAL NOISE;

CONTROL CURRENT; SUPERCONDUCTING DIGITAL CIRCUIT;

SUPERCONDUCTING DEVICES;

EID: 0032646030     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/77.783807     Document Type: Article

References (6)

1. Q. Herr and M. Feldman, "Error rate of a superconducting circuit," Appl. Phys. Lett., vol. 69, pp. 694-695, July 1996.
2. K. Likharev and V. Semenov, "RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems," IEEE Trans. Appl. Supercon., vol. 1, pp. 3-28, March 1991.
3. M. Tinkham, Introduction to Superconductivity. New York: McGraw-Hill, 2nd ed., 1996.
4. J. Satchell, "Margins and errors in SFQ circuits," Ext. Abstr. 6th Int. Supercand. Elec. Conf., vol. 1, pp. 44-46, June 1997.
5. c Josephson balanced comparator," unpublished.
6. Q. Herr and M. Feldman, "Error rate of RSFQ circuits: theory," IEEE Trans. Appl. Supercand., vol. 7, pp. 2661-2664, June 1997.